MT47H16M16BG-5E:B Micron Technology Inc, MT47H16M16BG-5E:B Datasheet - Page 35

• Manufacturer Part Number: MT47H16M16BG-5E:B
• Description: IC DDR2 SDRAM 256MBIT 5NS 84FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H16M16BG-5E:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock
19. The DRAM output timing is aligned to the nominal or average clock. Most output param-
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21.
22.
23. This is not a device limit. The device will operate with a negative value, but system per-
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-
26. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
27. The data valid window is derived by achieving other specifications:
28.
29. This maximum value is derived from the referenced test load.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential
that latches it in. However, the input timing (in ns) references to the
determining the required number of clocks. The following input parameters are deter-
mined by taking the specified percentage times the
t
eters must be derated by the actual jitter error when input clock jitter is present; this
will result in each parameter becoming larger. The following parameters are required to
be derated by subtracting
(MIN),
tracting
(MAX),
while
derated by subtracting
ty (MIN). Output timings that require
relative to the clock; however, the total window will not degrade.
t
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (
t
formance could be degraded due to bus turnaround.
The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were
previously in progress on the bus. If a previous WRITE was in progress, DQS could be
HIGH during this time, depending on
driven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if DQS
transitions HIGH (above V
to
x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
and
clock duty cycle and a practical data valid window can be derived.
t
t
and value of
data out window.
over
slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed:
and
values of
ues,
is referenced from V
referenced from V
tial DQS slew rate is not equal to 2 V/ns, then the baseline values must be derated by
adding the values from Table 30 (page 56) and Table 31 (page 57). If the DQS differ-
ential strobe feature is not enabled, then the DQS strobe is single-ended and the
baseline values must be derated using Table 32 (page 58). Single-ended DQS data tim-
ing is referenced at DQS crossing V
DIPW,
HZ and
LZ (MIN) will prevail over a
QH =
CH (ABS) MAX times
t
DQSH (MIN).
t
t
t
QH (
t
DS
DS
DQSCK (MAX) +
t
t
t
RPRE (MAX), is derated by subtracting
HP -
t
AON (MIN); while the following parameters are required to be derated by sub-
t
b
b
DQSS,
AON (MAX). The parameter
t
t
,
,
ERR
LZ transitions occur in the same access time windows as valid data transitions.
t
t
t
t
DS
QH =
DH
DH
t
QHS; the worst case
b
5per
t
b
b
JITdty will provide a larger
,
t
. The
, are the JEDEC-defined values, referenced from the logic trip points.
t
DQSH,
DH
t
HP -
(MIN):
IL(DC)
b
t
at V
IH(AC)
DS
t
t
QHS). The data valid window derates in direct proportion to the
t
t
CK (ABS) MIN -
DQSL,
RPST (MAX) condition.
a
t
for a rising signal and V
t
JITdty (MAX), while
,
AC (MAX),
REF
t
IH[DC]min
for a rising signal and V
35
DH
t
ERR
when the slew rate is 2 V/ns, differentially. The baseline val-
t
DQSCK (MIN) +
a
t
DSS,
values (for reference only) are equivalent to the baseline
5per
t
QH would be the lesser of
), then it must not transition LOW (below V
t
(MAX):
REF
t
t
DSH,
HZ) or begins driving (
AC Timing Operating Specifications
DQSCK (MAX),
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RPRE (MIN) is derated by subtracting
t
. The correct timing values for a single-ended DQS
t
t
QHS. Minimizing the amount of
ERR
DQSS.
256Mb: x4, x8, x16 DDR2 SDRAM
t
t
WPST, and
QH, which in turn will provide a larger valid
5per
t
AC (MIN),
t
t
RPST (MAX), is derated by subtracting
RPRE (MAX) condition.
t
JITper (MIN). The parameter
derating can be observed to have offsets
IH(DC)
IL(AC)
t
HZ (MAX),
t
for a falling signal. If the differen-
CK (AVG) rather than
t
WPRE.
t
DQSCK (MIN),
for a falling signal, while
t
LZ).
t
CL (ABS) MAX or
©2003 Micron Technology, Inc. All rights reserved.
t
HZ (MAX) will prevail
t
LZ
DQS
t
HP (
t
t
LZ
CK (AVG) when
(MAX),
t
DQS
CH (AVG) offset
t
CK/2),
t
t
t
(MIN),
JITper (MAX),
CK:
RPST (MIN) is
IH[DC]
t
LZ
t
DS
t
t
DQSQ,
IPW,
DQ
t
DH
a
) prior
t
,
LZ
t
t
JITd-
DH
t
b
DS
DQ
is
a
b