X28HC64JIZ-90 Intersil, X28HC64JIZ-90 Datasheet - Page 4

• Manufacturer Part Number: X28HC64JIZ-90
• Description: IC EEPROM 64KBIT 90NS 32PLCC
• Manufacturer: Intersil

Specifications of X28HC64JIZ-90

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DATA Polling (I/O
The X28HC64 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC64, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written
will produce the complement of that data on I/O
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
DATA Polling I/O
FIGURE 3. DATA POLLING SOFTWARE FLOW
A
0
–A
I/O
WE
OE
CE
12
7
SAVE LAST DATA
Write
AND ADDRESS
Last
COMPLETE?
READ LAST
7
COMPARE?
V
ADDRESS
An
)
WRITE DATA
IH
WRITES
READY
7
IO
7
YES
YES
4
An
7
NO
will reflect true data.
NO
HIGH Z
FIGURE 2. DATA POLLING BUS SEQUENCE
An
7
(i.e. write
V
OL
X28HC64
An
Toggle Bit (I/O
The X28HC64 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O
LOW to HIGH on subsequent attempts to read the device.
When the internal cycle is complete the toggling will cease
and the device will be accessible for additional read or write
operations.
DATA Polling can effectively reduce the time for writing to the
X28HC64. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
An
6
)
An
6
will toggle from HIGH to LOW and
An
V
X28HC64
Ready
OH
August 28, 2009
FN8109.2