AT45DB041B-RI Atmel, AT45DB041B-RI Datasheet - Page 5

• Manufacturer Part Number: AT45DB041B-RI
• Description: IC FLASH 4MBIT 20MHZ 28SOIC
• Manufacturer: Atmel

Specifications of AT45DB041B-RI

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 4M (2048 pages x 264 bytes)
• Speed: 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.1.2
5.1.3
5.1.4
3443D–DFLSH–2/08
Main Memory Page Read
Buffer Read
Status Register Read
A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
The maximum SCK frequency allowable for the Continuous Array Read is defined by the f
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
A Main Memory Page Read allows the user to read data directly from any one of the 2048 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device fol-
lowed by 24 address bits and 32 don’t care bits. The first four bits of the 24-bit address
sequence are reserved bits, the next 11 address bits (PA10 - PA0) specify the page address,
and the next nine address bits (BA8 - BA0) specify the starting byte address within the page.
The 32 don’t care bits which follow the 24 address bits are sent to initialize the read operation.
Following the 32 don’t care bits, additional pulses on SCK result in serial data being output on
the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data. When the end of a page in main mem-
ory is reached during a Main Memory Page Read, the device will continue reading at the
beginning of the same page. A low-to-high transition on the CS pin will terminate the read oper-
ation and tri-state the SO pin.
Data can be read from either one of the two buffers, using different opcodes to specify which
buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode
of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the
opcode must be followed by 15 don’t care bits, nine address bits, and eight don’t care bits. Since
the buffer size is 264 bytes, nine address bits (BFA8 - BFA0) are required to specify the first byte
of data to be read from the buffer. The CS pin must remain low during the loading of the opcode,
the address bits, the don’t care bits, and the reading of data. When the end of a buffer is
reached, the device will continue reading back at the beginning of the buffer. A low-to-high tran-
sition on the CS pin will terminate the read operation and tri-state the SO pin.
The status register can be used to determine the device’s Ready/Busy status, the result of a
Main Memory Page to Buffer Compare operation, or the device density. To read the status reg-
ister, an opcode of 57H or D7H must be loaded into the device. After the last bit of the opcode is
shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on
the SO pin during the next eight clock cycles. The five most significant bits of the status register
will contain device information, while the remaining three least-significant bits are reserved for
future use and will have undefined values. After bit 0 of the status register has been shifted out,
the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting
again with bit 7. The data in the status register is constantly updated, so each repeating
sequence will output new data.
Table 5-1.
RDY/BUSY
Bit 7
Status Register Format
COMP
Bit 6
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
1
AT45DB041B
Bit 1
X
Bit 0
X
CAR
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