MT45W4MW16BCGB-701 WT Micron Technology Inc, MT45W4MW16BCGB-701 WT Datasheet - Page 15

• Manufacturer Part Number: MT45W4MW16BCGB-701 WT
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 WT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9:
Mixed-Mode Operation
WAIT Operation
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Burst Mode WRITE (4-Word Burst)
Note:
DQ[15:0]
The device supports a combination of synchronous READ and asynchronous READ and
WRITE operations when the BCR is configured for synchronous operation. The asyn-
chronous READ and WRITE operations require that the clock (CLK) remain LOW during
the entire sequence. The ADV# signal can be used to latch the target address, or it can
remain LOW during the entire WRITE operation. CE# can remain LOW when transi-
tioning between mixed-mode operations with fixed latency enabled; however, the CE#
LOW time must not exceed
to legacy burst mode Flash memory controllers. See Figure 50 on page 63 for the “Asyn-
chronous WRITE Followed by Burst READ” timing diagram.
The WAIT output on a CellularRAM device typically is connected to a shared, system-
level WAIT signal (see Figure 10 on page 16). The shared WAIT signal is used by the
processor to coordinate transactions with multiple memory devices on the synchronous
bus.
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
Nondefault BCR settings for burst mode WRITE (4-word burst): fixed or variable latency;
latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
CLK
CE#
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
WRITE burst identified
address
(WE# = LOW)
Valid
Latency code 2 (3 clocks)
t
CEM. Mixed-mode operation facilitates a seamless interface
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D0
D1
Bus Operating Modes
©2005 Micron Technology, Inc. All rights reserved.
D2
Don’t Care
D3