W25P16VSSIG Winbond Electronics, W25P16VSSIG Datasheet
W25P16VSSIG
Specifications of W25P16VSSIG
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W25P16VSSIG Summary of contents
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... AND 16M-BIT SERIAL FLASH MEMORY Formally NexFlash NX25P80 and NX25P16 The Winbond W25P80/16 are fully compatible with the previous NexFlash NX25P80/16 Serial Flash memories. W25P80 AND W25P16 Publication Release Date: January 19, 2007 - 1 - Revision M ...
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... BUSY..............................................................................................................................10 9.1.2 Write Enable Latch (WEL) ..............................................................................................10 9.1.3 Block Protect Bits (BP2, BP1, BP0)................................................................................11 9.1.4 Reserved Bits .................................................................................................................11 9.1.5 Status Register Protect (SRP)........................................................................................11 9.1.6 Status Register Memory Protection ................................................................................12 9.2 INSTRUCTIONS........................................................................................................... 13 9.2.1 Manufacturer and Device Identification ..........................................................................13 9.2.2 Instruction Set 9.2.3 Write Enable (06h)..........................................................................................................15 9.2.4 Read Status Register (05h) ...
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Page Program (02h) .......................................................................................................20 9.2.9 Sector Erase (D8h).........................................................................................................21 9.2.10 Chip Erase (C7h)..........................................................................................................22 9.2.11 Power-down (B9h) ........................................................................................................23 9.2.12 Release Power-down / Device ID (ABh) .......................................................................23 9.2.13 Read Manufacturer / Device ID (90h) ...........................................................................25 9.2.14 JEDEC ID (9Fh) ...........................................................................................................26 9.2.15 Read ...
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... Sector Erase (64K-byte) 0.6 seconds – 100,000 erase/write cycles – Twenty-year data retention • Software and Hardware Write Protection – Write-Protect all or portion of memory – Enable/Disable protection with /WP pin • Parameter Page – 256 Byte page for ID# revision# or configuration data – ...
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PIN CONFIGURATION 208-MIL Figure 1a. W25P80/16 Pin Assignments, 8-pin SOIC 208-mi 4. PIN DESCRIPTION 208-MIL PIN NO. PIN NAME 1 / /WP 4 GND CLK 7 /HOLD 8 VCC W25P80 AND W25P16 I/O ...
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PIN CONFIGURATION 300-MIL Figure 1b. W25P16 Pin Assignments, 16-pin SOIC 300-mil 6. PIN DESCRIPTION 300-MIL PAD NO. PAD NAME 1 /HOLD 2 VCC 3 N/C 4 N/C 5 N/C 6 N /WP 10 GND ...
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... The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. ...
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BLOCK DIAGRAM W25P80 AND W25P16 Figure 2. W25P80 and W25P16 Block Diagram - 8 - ...
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... WRITE PROTECTION Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the W25P80/16 provides several means to protect data from inadvertent writes. ...
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... Status Register Protect (SRP) and Block Protect (BP2, BP1, and BP0) bits. These Status Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...
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... S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see t can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. The Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low ...
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... Upper 1/32 1M-bit Upper 1/16 2M-bit Upper 1/8 4M-bit Upper 1/4 8M-bit Upper 1/2 All memory plus Parameter Page DENSITY (KB) PORTION NONE NONE 512K-bit Upper 1/16 1M-bit Upper 1/8 2M-bit Upper 1/4 4M-bit Upper 1/2 All memory plus Parameter Page ...
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... Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...
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... A7–A0 Don’t care Don’t care A7–A0 Don’t care Don’t care A7–A0 dummy dummy dummy dummy dummy 00h (ID15-ID8) (M7-M0) (ID7-ID0) Memory Manufacturer Capacity Type - 14 - BYTE 5 BYTE 6 N-BYTES (2) (D7–D0) (Next byte) continuous (Next Byte) dummy (D7–D0) continuous ...
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Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register The WEL bit must be set prior to every Page Program, Sector Erase, Chip Erase and ...
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Read Status Register (05h) The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” into the DI pin on the rising edge ...
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... The Write Status Register instruction allows the Block Protect bits (BP2, BP1 and BP0 set for protecting all, a portion, or none of the memory from erase and program instructions. Protected areas become read-only (see Status Register Memory Protection table). The Write Status Register instruction also allows the Status Register Protect bit (SRP set ...
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... DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F “dummy” byte after the 24-bit address as shown in figure 9. The dummy ...
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... Page Program (02h) The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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... Sector Erase (D8h) The Sector Erase instruction sets all memory within a specified sector to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Erase Sector Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Chip Erase (C7h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in figure 13, except that after /CS is driven high it must remain high for ...
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Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ...
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... Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 17. For the W25P80, the Memory Type is 20h and the Capacity is 14h. For the W25P16, the Memory type is also 20h and the Capacity is 15h. ...
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... CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data ...
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Fast Read Parameter Page (5Bh) The Fast Read Parameter Page instruction is basically the same as the Read Parameter Page instruction except that it allows for a faster clock rate to be used. The Fast Read Parameter Page instruction ...
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... Program Parameter Page (52h) The Program Parameter Page instruction allows up to 256 bytes (128 words programmed at memory word locations that have been previously erased to all 1s “FFFFh” (see Erase Parameter Page instruction). A Write Enable instruction must be executed before the device will accept the Program Parameter Page instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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Figure 20. Parameter Page Program Instruction Sequence Diagram - 30 - W25P80 AND W25P16 ...
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... Erase Parameter Page (D5h) The Erase Parameter Page instruction sets all 256 bytes of memory in the Parameter Page to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Erase Parameter Page instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of ...
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Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. W25P80 AND W25P16 SYMBOL MIN t (1) VSL t (1) PUW ...
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DC Electrical Characteristics (Preliminary) PARAMETER SYMBOL Input Capacitance C (2) IN Output Capacitance Cout (2) Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data ...
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AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. W25P80 AND W25P16 SYMBOL C ...
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AC Electrical Characteristics DESCRIPTION Clock frequency, for Fast Read (0Bh) and all other instructions except Read Data (03h) 2.7V-3.6V VCC 3.0V-3.6V VCC Clock freq. Read Data instruction 03h Clock High, Low Time, for Fast Read (0Bh) and all other ...
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AC Electrical Characteristics, continued DESCRIPTION /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z /HOLD to Output High-Z Write Protect Setup Time Before /CS Low Write Protect Hold Time ...
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Serial Output Timing 10.8 Input Timing 10.9 Hold Timing W25P80 AND W25P16 - 38 - ...
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PACKAGE SPECIFICATION 11.1 8-Pin SOIC 208-mil (Winbond Package Code SS) SYMBOL θ y Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. ...
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SOIC 300-mil (Winbond Package Code SF) SYMBOL ( ( θ y Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. ...
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ORDERING INFORMATION 1. The Winbond W25P80/16 are fully compatible with the previous NexFlash NX25P80/16 Serial Flash Memories. The “W” prefix is not included on the part marking. 2. Only the second letter is used for part marking. 3. Standard ...
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... Updated dimensional table for the 208milSOIC in the packaging information. Added 208milSOIC and removed 5x6mm MLP for W25P16. Added Parameter Page data to Features, Block Diagram (Figure 2), Status Register Memory Protection, Instruction Set and Manufacturer and Device Identification. Added Parameter Page timing diagrams (Figures 20, 21, 22 and 23). Updated F ...
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Preliminary Designation The “Preliminary” designation on a Winbond data sheet indicates that the product is not fully characterized. The specifications are subject to change and are not g authorized sales representative should be consulted for current information before using this ...