MD2533-D8G-X-P SanDisk, MD2533-D8G-X-P Datasheet - Page 49

• Manufacturer Part Number: MD2533-D8G-X-P
• Description: IC MDOC H3 8GB FBGA
• Manufacturer: SanDisk

Specifications of MD2533-D8G-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

7.3.15 DMA Control Register
Description:
Address (hex): 940E (128KB window) / 140E (8KB window)
Type:
Note: This register cannot be accessed when the A0 signal is pulled high. Therefore it is
7.3.16 DMA Negation Register
Description:
Address (hex): 9418 (128KB window) / 1418 (8KB window)
Type:
49
Bit number
Read/Write R
Bit name
Reset value
PULSE_WIDTH
EDGE
DMA_POL
DMA_EN
recommended that A0 will be connected to Host CPU A0, or to VSS.
D15-D9
RFU
0
This 16-bit register controls the DMA_REQ signal to the host.
Read / Write
This 16-bit register controls the negation of DMARQ# signal to the host.
Read / Write
The width of the DMARQ# signal will be:
PULSE_WIDTH * ICMU_CLK (cycle). Maximum 32 ICMU clocks.
Note: If the value is zero then DMARQ# signal will not be asserted.
Level or Edge:
0: Level – DMARQ# will be asserted when data is ready and will be
de-asserted before the end of the data according to DMA_PROG_NEG
(DMA Negation Register).
1: Edge – DMARQ# will be generated for the number of clock
specified in the PULSE_WIDTH field.
DMARQ# polarity:
0: active high
1: active low
DMA enable bit:
0: DMARQ# is disabled
1: DMARQ# is enabled
D8-D4
R/W
PULSE_WIDTH RFU
4
Data Sheet (Preliminary) Rev. 0.2
D3
R
0
D2
R/W
EDGE
0
D1
R/W
DMA_POL
1
mDOC H3 Embedded Flash Drive
D0
R/W
DMA_EN
0
92-DS-1205-10