MD2533-D8G-X-P SanDisk, MD2533-D8G-X-P Datasheet - Page 59

• Manufacturer Part Number: MD2533-D8G-X-P
• Description: IC MDOC H3 8GB FBGA
• Manufacturer: SanDisk

Specifications of MD2533-D8G-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

• BUSY# (Busy) – This signal indicates when the device is ready for first access after reset. It
• DMARQ# (DMA Request) – Output used to control multi-page DMA operations. Connect
• IRQ# (Interrupt Request) – Connect this signal to the host interrupt.
• Lock# (LOCK) – Connect to a logical 0 to prevent the usage of the protection key to open a
• CLK (Clock) – This input is used to support Burst operation when reading flash data. Refer to
• WARM_RST# (Warm Reset) - The warm reset input is used to reset only the host interface
9.6.2
mDOC H3 can use a multiplexed interface to connect to a multiplexed bus. In this configuration,
mDOC H3 AVD# signal is driven by the host's AVD# signal, and the D[15:0] balls, used for both
address inputs and data, are connected to the host AD[15:0] bus.
This mode is automatically entered when a falling edge is detected on AVD#. This edge must
occur after RSTIN# is negated and before OE# and CE# are both asserted; i.e., the first read cycle
made to mDOC must observe the multiplexed mode protocol. See Section 10 for more
information about the related timing requirements.
Please refer to Section 2.3 for ballout and signal descriptions, and to Section 10 for timing
specifications for a multiplexed interface.
9.7
9.7.1 Hardware Configuration
To configure the hardware for working with the interrupt mechanism, the IRQ# ball should be
connected to a host interrupt input.
9.7.2
IRQ# signal may be used by mDOC H3 to interrupt the host system, provided that device
interrupts are enabled. Interrupts can be enabled or disabled by writing the nIEN bit in the Device
Control register. IRQ# signal behavior (active high/low, edge/level) must be configured during
device formatting, using the appropriate low level format utilities such ad DOCFORMAT and
DOC driver format API.
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may be connected to an input port of the host, or alternatively it may be used to hold the host
in a wait-state condition. The later option is required for hosts that boot from mDOC H3.
this output to the DMA controller of the host platform.
protected partition. Connect to logical 1 in order to enable usage of protection keys.
Section 9.8 for further information on Burst operation.
block. This option is to be used in case the host experienced a reset which mDOC H3 is not
exposed to for any reason. For example in case of watchdog reset in specific platforms, GPIO
reset etc. It is recommended to connect this input to system nRESET_OUT signal if available
or to a host GPIO in other cases. Upon assertion of the warm reset signal mDOC H3 host
interface will switch to a pre-defined state according to the data written in a dedicated control
register (refer to Warm Boot Register for detailed description). The configurable operation of
the warm boot input allows mDOC H3 to be connected to all of the platforms without being
stacked by any kind of reset.
Multiplexed Interface
Implementing the Interrupt Mechanism
Software Configuration
Data Sheet (Preliminary) Rev. 0.2
mDOC H3 Embedded Flash Drive
92-DS-1205-10