MD2533-D8G-X-P SanDisk, MD2533-D8G-X-P Datasheet - Page 61

• Manufacturer Part Number: MD2533-D8G-X-P
• Description: IC MDOC H3 8GB FBGA
• Manufacturer: SanDisk

Specifications of MD2533-D8G-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

4.
5. Program host DMA controller to transfer the same number of sectors as will be given in
6. Issue the DMA data-transfer read/write command with same number of sectors to transfer as
Upon command completion IRQ# will be asserted (it is recommended to use IRQ# when working
with DMA). In case of a failure, less than expected amount of data could be transferred.
In commands that use DMA transfer, IRQ# is activated only at the completion of the whole
command; while in commands that do not use DMA transfer IRQ# is typically activated with
every data transfer.
In case DMA transfer needs to be aborted, SRST should be set in the Device Control register, in
order to abort the command. After this wait until mDOC H3 is no longer BUSY.
Default setting of DMARQ# is level and active-low. It can be modified at programming /
formatting stage.
9.8.2
Burst operation is especially effective for large file reads that are typical during boot-up. Data is
read by the host one 16-bit word after another using the CLK input.
Burst operation is controlled by 5 bit fields in each Burst Mode Control register (one for Burst
read and one for Burst write): BURST_EN, WAIT_STATE, LATENCY, HOLD and LENGTH.
For full details on this register, please refer to Section 6.5.
Burst Read / Write mode is enabled by setting the BURST_EN bit in each Burst Mode Control
register.
The HOLD bit in the Burst Mode Control register can be set to hold each data word valid for two
clock cycles rather than one.
The LENGTH field must be programmed with the length of the burst to be performed (0
corresponds to 4 cycles; 1 to 8 cycles, 2 to 16 and 3 corresponds to 32 cycles). Each burst cycle
must read exactly this number of words.
WAIT_STATE allows setting the number of CLK after the host has read the [N-1] word until the
assertion of the CE#.
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If host DMA controller detects the de-assertion of the DMARQ# signal too late (and
attempts to transfer additional words as a result), then DMARQ# can be configured to be de-
asserted earlier by using the DMA Negation Register.
following logical command.
given in the previous step (prior to this, the device should be instructed to perform transfers
in DMA-mode).
• 0: None – No CLK before CE# assertion.
• 1: One CLK clock before CE# assertion.
• 2: Two CLK clocks before CE# assertion.
• 3: Three CLK clocks before CE# assertion.
Burst Operation
Data Sheet (Preliminary) Rev. 0.2
mDOC H3 Embedded Flash Drive
92-DS-1205-10