ISL6251HRZ-T Intersil, ISL6251HRZ-T Datasheet
ISL6251HRZ-T
Specifications of ISL6251HRZ-T
Related parts for ISL6251HRZ-T
ISL6251HRZ-T Summary of contents
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... TEMP NUMBER PART RANGE (Notes 1, 2) MARKING (°C) ISL6251HRZ ISL6251HRZ -10 to 100 28 Ld 5x5 QFN L28.5×5 ISL6251HAZ ISL6251HAZ -10 to 100 24 Ld QSOP ISL6251AHRZ ISL6251AHRZ -10 to 100 28 Ld 5x5 QFN L28.5×5 ISL6251AHAZ ISL6251AHAZ -10 to 100 24 Ld QSOP NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets ...
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Pinouts ISL6251, ISL6251A (28 LD QFN) TOP VIEW CELLS 2 ICOMP 3 VCOMP 4 ICM 5 VREF 6 CHLIM ISL6251, ISL6251A 23 22 CSOP 21 CSIN ...
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Absolute Maximum Ratings DCIN, CSIP, CSON to PGND . . . . . . . . . . . . . . . . . . . -0.3V to +28V CSIP-CSIN, CSOP-CSON . . . . . . . . ...
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Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C ≤ 125°C, unless ...
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Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C ≤ 125°C, unless ...
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Typical Operating Performance 0.6 0.6 0.3 0 -0.3 -0.3 -0.6 -0 LOAD CURRENT (mA) LOAD CURRENT (mA) FIGURE 1. VDD LOAD REGULATION ...
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Typical Operating Performance BATTERY BATTERY INSERTION INSERTION VCOMP VCOMP ICOMP ICOMP FIGURE 7. BATTERY INSERTION AND REMOVAL FIGURE 9. SWITCHING WAVEFORMS IN CC MODE 7 ISL6251, ISL6251A DCIN = 20V, 4S2P Li-Battery, T INDUCTOR INDUCTOR CURRENT CURRENT 2A/div 2A/div BATTERY ...
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Functional Pin Descriptions BOOT Connect BOOT to a 0.1µF ceramic capacitor to PHASE pin and connect to the cathode of the bootstrap schottky diode. UGATE UGATE is the high side MOSFET gate drive output. LGATE LGATE is the low side ...
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ISL6251, ISL6251A ICM ICM ACSET ACSET ACPRN ACPRN + + - - 1.26V 1.26V VREF VREF VREF VREF + + + - - - 152K 152K 152K 152K Adapter Adapter 1.27V 1.27V Current Current ACLIM ACLIM Limit Set Limit Set ...
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AC ADAPTER R8 D3 130k 1% R9 DCIN DCIN 10.2k 1% ACSET ACSET C7 C7 1µF VDDP VDDP R10 3.3V 4.7Ω VDD VDD C9 R5 1µF 100k To Host ACPRN ACPRN Controller C6:6.8nF ICOMP ICOMP R6:10k C5:10nF VCOMP VCOMP FLOATING ...
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AC ADAPTER R8 130k 1% R9 10.2k,1% C7 R10 1µF 4.7Ω VCC R5 C9 DIGITAL 100k 1µF INPUT D/A OUTPUT OUTPUT R7: 100Ω A/D INPUT C11 3300pF 5.15A INPUT CURRENT LIMIT C6 HOST 6.8nF R6 C5 10k 10nF AVDD/VREF R11, ...
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Theory of Operation Introduction The ISL6251, ISL6251A includes all of the functions necessary to charge cell Li-Ion and Li-polymer batteries. A high efficiency synchronous buck converter is used to control the charging voltage and charging current up ...
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R and R are external resistors at bot_VADJ top_VADJ VADJ. To minimize accuracy loss due to interaction with VADJ’s internal resistor divider, ensure the AC resistance looking back into the external resistor divider is less than 25k. Connect CELLS ...
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A low pass filter is suggested to eliminate the switching noise. Connect the resistor to CSIN pin instead of CSIP pin because CSIN pin has lower bias current and less influence on the current-sense accuracy. AC Adapter Detection Connect the ...
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The core must be large enough not to saturate at the peak inductor current I 1 Δ Peak BAT , MAX L 2 Output Capacitor Selection The output capacitor ...
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As a general rule, select a diode with DC current rating equal to one-third of the load current. One option is to choose a combined MOSFET with the Schottky diode in a single package. The integrated packages may work better ...
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Current loop gain T (S) is expressed as the following i equation 0. where R is the trans-resistance in current loop usually equal to the ...
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PCB Layout Considerations Power and Signal Layers Placement on the PCB As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. ...
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... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389 Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...