PCA9634PW,112 NXP Semiconductors, PCA9634PW,112 Datasheet - Page 21

• Manufacturer Part Number: PCA9634PW,112
• Description: IC LED DRIVER RGBA 20-TSSOP
• Manufacturer: NXP Semiconductors
• Type: RGBA LED Driverr

Specifications of PCA9634PW,112

• Package / Case: 20-TSSOP
• Topology: Open Drain, PWM
• Number Of Outputs: 8
• Internal Driver: Yes
• Type - Primary: Backlight, LED Blinker
• Type - Secondary: RGBA
• Frequency: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Voltage - Output: 5.5V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 25mA
• Internal Switch(s): Yes
• Low Level Output Current: 25 mA
• High Level Output Current: 50 uA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 10 mA
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Details
• Other names: 935282233112; PCA9634PW; PCA9634PW

NXP Semiconductors
PCA9634_6
Product data sheet
Fig 11. System configuration
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 12. Acknowledgement on the I
RECEIVER
SLAVE
SCL from master
by transmitter
data output
by receiver
data output
Rev. 06 — 12 September 2008
TRANSMITTER/
RECEIVER
condition
START
SLAVE
S
2
C-bus
TRANSMITTER
1
MASTER
2
TRANSMITTER/
RECEIVER
MASTER
acknowledgement
not acknowledge
SLAVE
clock pulse for
8-bit Fm+ I
acknowledge
8
MULTIPLEXER
PCA9634
2
© NXP B.V. 2008. All rights reserved.
C-bus LED driver
002aaa987
I
2
9
C-BUS
002aaa966
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