ISL6594ACBZ Intersil, ISL6594ACBZ Datasheet - Page 8

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ISL6594ACBZ

Manufacturer Part Number
ISL6594ACBZ
Description
IC MOSFET DRVR SYNC BUCK 8-SOIC
Manufacturer
Intersil
Datasheet

Specifications of ISL6594ACBZ

Configuration
High and Low Side, Synchronous
Input Type
PWM
Delay Time
10.0ns
Current - Peak
1.25A
Number Of Configurations
1
Number Of Outputs
2
High Side Voltage - Max (bootstrap)
36V
Voltage - Supply
10.8 V ~ 13.2 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively:
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs; N
and N
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
(R
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as shown in Equation 4:
P
P
P
P
R
I
Qg_TOT
DR
DR
DR_UP
DR_LOW
EXT1
GI1
P
P
=
=
Q2
Qg_Q1
Qg_Q2
and R
P
=
Q
----------------------------------------------------- -
DR_UP
=
are number of upper and lower MOSFETs,
=
R
G1
=
G1
G1
P
GI2
--------------------------------------
R
=
=
Qg_Q1
HI1
--------------------------------------
R
+
UVCC N
and R
V
HI2
Q
-------------------------------------- - f
Q
------------------------------------- - f
) of MOSFETs. Figures 3 and 4 show the
+
R
-------------
GS1
R
N
G1
G2
+
P
GI1
HI1
Q1
R
R
+
DR_LOW
V
V
HI2
+
EXT1
R
GS2
GS1
G2
P
UVCC
LVCC
EXT2
Qg_Q2
) and the internal gate resistors
Q1
G1
+
+
+
+
2
--------------------------------------- -
R
2
and Q
I
Q
---------------------------------------------------- -
LO1
--------------------------------------- -
R
+
Q
R
8
LO2
G2
EXT2
I
SW
SW
Q
R
VCC
+
LO1
R
+
R
LO2
VCC
LVCC N
GS1
G2
V
N
N
EXT1
R
GS2
Q
=
Q2
Q1
) is defined at a
EXT2
R
and V
is the driver’s total
G2
+
P
---------------------
Q2
GS2
R
-------------
Qg_Q1
N
P
---------------------
Q*
GI2
Q2
Qg_Q2
2
2
VCC
) in the
f
SW
ISL6594A, ISL6594B
(EQ. 2)
(EQ. 3)
(EQ. 4)
+
Q1
I
Q
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
UVCC
LVCC
PHASE
R
R
BOOT
LO2
R
HI2
R
LO1
HI1
R
G2
R
G
G1
G
R
C
GI2
R
GD
C
C
GI1
GD
GS
C
GS
S
S
D
December 3, 2007
D
Q2
C
Q1
DS
C
FN9157.5
DS

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