L9848 STMicroelectronics, L9848 Datasheet - Page 16

• Manufacturer Part Number: L9848
• Description: IC DRIVER LO/HI SIDE OCTAL 28SOI
• Manufacturer: STMicroelectronics
• Type: High Side/Low Side Driverr

Specifications of L9848

• Input Type: SPI
• Number Of Outputs: 8
• Current - Output / Channel: 800mA
• Current - Peak Output: 1.3A
• Voltage - Supply: 4.75 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: SO-28
• Rise Time: 30 ns
• Fall Time: 30 ns
• Supply Voltage (min): 4.75 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• On-state Resistance: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Functional description
3.5.1
3.5.2
3.5.3
3.5.4
16/27
Serial data output (DO)
This output pin is in a tri-state condition when CS is a logic "0" (LOW). When CS is a logic
"1" (HIGH), this pin always transmits 8bits of data from the fault register to the digital
controller. After the first 8bits data are transmitted the DO output then sequentially transmits
the digital data that was just received (8 SCLK cycles earlier) on the DI pin. The DO output
continues to transmit the 8 SCLK delayed bit data from the DI input until CS eventually
transitions from a logic "1" to a logic "0". DO data changes state 10 ns or later, after the
falling edge of SCLK. By definition, the MSB (Table 3) is the first bit of the byte transmitted
on DO and the LSB is the last bit of the byte transmitted on DO, once CS transitions from a
logic "0" to a logic "1".
Serial data input (DI)
This input takes data from the digital controller while CS is HIGH. The L9848 accepts an 8bit
data stream to command the outputs ON or OFF. By definition, the MSB (Table 1) is the first
bit of each byte received on DI and the LSB is the last bit of each byte received on DI, once
CS transitions from a logic "0" to a logic "1".
Chip select (CS)
This is the chip select input pin. On the rising edge of CS, the DO pin switches from tri-state
to active-out mode. While CS is high, register data is shifted in and shifted out by the DI and
DO pin, respectively, on each subsequent SCLK. On the falling edge of CS, the DO pin
switches back to tri-state mode and the fault register will be "Cleared" if a valid DI byte was
received.
A valid DI byte is defined as such:
The fault data is not cleared unless all of the 3 previous conditions have been met. A SCLK
transition must be seen before CS is interpreted as active. To allow sufficient time to reload
the fault registers, the CS pin must remain low for a minimum of 1µs prior to going high
again, before it starts shifting the fault data bits out on the DO pin. CS has an integrated
glitch filter for spurious pulses of 50ns or shorter (i.e. no fault data and Outputs1-8 enable
status will be altered). For open circuit condition the CS is internally pulled down to GND.
Serial clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into
the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.
1
2
3
st
nd
rd
A multiple of 8 bits was received
SCLK was low when CS went low
Current SPI cycle started when SCLK was low
L9848