L9848 STMicroelectronics, L9848 Datasheet - Page 17

• Manufacturer Part Number: L9848
• Description: IC DRIVER LO/HI SIDE OCTAL 28SOI
• Manufacturer: STMicroelectronics
• Type: High Side/Low Side Driverr

Specifications of L9848

• Input Type: SPI
• Number Of Outputs: 8
• Current - Output / Channel: 800mA
• Current - Peak Output: 1.3A
• Voltage - Supply: 4.75 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: SO-28
• Rise Time: 30 ns
• Fall Time: 30 ns
• Supply Voltage (min): 4.75 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• On-state Resistance: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

L9848
3.6
3.7
SPI DI input command register
An input byte (8 bits) is routed to the Command Register. The content of this Command
Register is given in
around to the DO pin. If CS will go low before a complete reception of the current byte, this
just transmitted byte will be ignored
Table 8.
Table 9.
Fault operation
The fault diagnostic capability consists of one internal 8bit shift register. Open or shorted
load detection is provided by comparing the source or drain voltage with the VDD voltage.
When an output connected as either a low side device or a high side device is commanded
OFF, an open load can be detected. When an output connected as either a low side device
or a high side device is commanded ON a shorted load can be detected.
The fault bit is "set" for each channel if a short, open, or over-temperature condition occurs
for Outputs1-8. The content of this Fault Register is given in
The output load status of each individual channel is defined in
are subsequently re-latched provided they meet the minimum duration criterion and thermal
faults will be re-latched provided they meet the duration criterion after CS goes "LOW", if
these fault conditions are still present.
The fault register is capable of detecting and latching multiple fault conditions (among the 8
outputs) that have occurred between clearing of the fault flags.
All of the faults will be cleared on the falling edge of Chip Select (CS).
Table 10.
Table 11.
D00-D07
D00-D07
Fault1-8
Fault1-8
Fault8
OUT8
MSB
MSB
D07
D07
Bit
BIT
Bit command register definition
Command register logic definition
Fault register definition
Fault logic definition
State
Fault7
D06
STATE
OUT7
0
1
D06
0
1
Table 8
OUTPUT1-8 are commanded OFF
OUTPUT1-8 are commanded ON
OUT1-8 are not open or shorted (nominal)
OUT1-8 are either open or shorted or in thermal shutdown
Fault6
D05
OUT6
D05
and
Table
Fault5
D04
OUT5
9. Additional DI data will continue to be wrapped
D04
Fault4
D03
OUT4
D03
Status
STATUS
Fault3
D02
OUT3
Table
D02
Table
10.
Fault2
Functional description
D01
11. Open and shorts
OUT2
D01
Fault1
LSB
D00
OUT1
LSB
D00
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