MC33887AVW Freescale Semiconductor, MC33887AVW Datasheet - Page 3

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MC33887AVW

Manufacturer Part Number
MC33887AVW
Description
IC H-BRIDGE LOAD CURR FB 20-HSOP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC33887AVW

Applications
DC Motor Controller, H Bridge
Number Of Outputs
1
Current - Output
5A
Voltage - Supply
5 V ~ 28 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-HSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Load
-

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Table 1. 33887 HSOP PIN DEFINITIONS
Analog Integrated Circuit Device Data
Freescale Semiconductor
A functional description of each pin can be found in the
Tab/Pad
4 , 5, 16
14 , 15
9 – 12
6 , 7
Pin
13
17
18
19
20
1
2
3
8
Pin Name
Interface
Thermal
AGND
PGND
OUT1
OUT2
CCP
IN1
IN2
EN
FS
V+
FB
D2
D1
Fault Status for H-Bridge
Charge Pump Capacitor
Feedback for H-Bridge
Positive Power Supply
Exposed Pad Thermal
Logic Input Control 1
Logic Input Control 2
H-Bridge Output 1
H-Bridge Output 2
Analog Ground
Power Ground
Formal Name
Disable 2
Disable 1
Interface
Enable
AGND
PGND
PGND
OUT1
OUT1
IN1
V+
FS
V+
FB
Figure 3. 33887 Pin Connections
PIN CONNECTIONS
1
2
3
4
5
6
7
8
9
10
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Positive supply connections
Output 1 of H-Bridge.
Current sensing feedback output providing ground referenced 1/375th
(0.00266) of H-Bridge high-side current.
High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
External reservoir capacitor connection for internal charge pump capacitor.
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN
logic LOW = Sleep Mode).
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
Functional Pin DescriptionS
Tab
Tab
20
19
18
17
16
15
14
13
12
11
EN
IN2
D1
CCP
V+
OUT2
OUT2
D2
PGND
PGND
section,
Definition
page
21.
PIN CONNECTIONS
33887
3

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