L6563 STMicroelectronics, L6563 Datasheet - Page 21

• Manufacturer Part Number: L6563
• Description: IC PFC CTRLR TRANSITION 14SOIC
• Manufacturer: STMicroelectronics

Specifications of L6563

• Mode: Discontinuous (Transition)
• Current - Startup: 50µA
• Voltage - Supply: 10.3 V ~ 22 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 25 C
• For Use With: 497-9082 - EVAL BOARD L6563 (200W)497-8850 - BOARD EVAL FOR L6563/STW55NM60N497-8834 - BOARD DEMO FOR L6563/LL6566A497-8429 - BOARD ADAPTER L6599/STP12NM50N497-5854 - DEMO BOARD FOR L6563497-5496 - EVAL BOARD FOR L6599497-5493 - EVAL BOARD FOR L6563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Switching: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

L6563 - L6563A
6.4
THD optimizer circuit
The L6563/A is provided with a special circuit that reduces the conduction dead-angle
occurring to the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the high-
frequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This will result in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.
Figure 37 shows the internal block diagram of the THD optimizer circuit.
Figure 37. THD optimizer circuit
@ Vac1
@ Vac1
@ Vac2 > Vac1
@ Vac2 > Vac1
MULT
MULT
t
t
t
t
VFF
VFF
1 / V
1 / V
1 / V
GENERATOR
GENERATOR
GENERATOR
2
2
2
MULTIPLIER
MULTIPLIER
MULTIPLIER
OFFSET
OFFSET
OFFSET
COMP
COMP
t
t
+
+
+
+
t
t
comparator
comparator
Application information
to PWM
to PWM
t
t
t
t
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