NCP1631DR2G ON Semiconductor, NCP1631DR2G Datasheet - Page 11

• Manufacturer Part Number: NCP1631DR2G
• Description: IC CTLR PFC INTERLEAVED 16SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1631DR2G

• Mode: Critical Conduction (CRM), Discontinuous Conduction (DCM)
• Frequency - Switching: 130kHz
• Current - Startup: 100µA
• Voltage - Supply: 10 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Regulation Block and Low Output Voltage Detection
inverting input and output is provided. It features a typical
trans−conductance gain of 200 mS and a typical capability
of ±20 mA. The output voltage of the PFC stage is typically
scaled down by a resistors divider and monitored by the
inverting input (feed−back pin – pin2). The bias current is
minimized (less than 500 nA) to allow the use of a high
impedance feed−back network. The output of the error
amplifier is pinned out for external loop compensation
(pin5). Typically a type−2 compensator is applied between
pin5 and ground, to set the regulation bandwidth below
20 Hz, as need in PFC applications (refer to application
note AND8407).
Figure 8. Input Voltage and On−time vs. Time (example with F
A trans−conductance error amplifier with access to the
350,00
300,00
250,00
200,00
150,00
100,00
V control
50,00
0,00
FB
0
Figure 9. Regulation Block
0.955*Vref
Vout low
detect
OVLflag1
Vref
OFF
2
E rr o r Am p lifier
−
−
+
+
3V
pfcOK
4
±20 m A
5R
4R
6
SKIP
V
230 m A
REGUL
vo ltage is activated)
(0 .6 V c lamp
VDD
8
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time (ms)
11
10
an accurate range:
•
•
Hence, V
offset down by (V
to the “V
Finally, the output of the regulation is a signal (“V
of the block diagram) that varies between 0 and 1.66 V.
SW
The swing of the error amplifier output is limited within
It is forced above a voltage drop (V
clamp” circuitry. When this circuitry is activated, the
power demand is minimum and the NCP1631 enters
skip mode (the controller stops pulsating) until the
clamp is no more active.
It is clamped not to exceed 3.0 V + the same V
voltage drop.
= 100 kHz, Pin = 150 W, V
12
pin5
ton
Figure 10. Correspondence Between
features a 3 V voltage swing. V
processing block” and the PWM section.
14
F
) and further divided before it connects
V
CONTROL
Vin
ton
16
and V
AC
= 230 V, L = 200 mH)
REGUL
18
F
) by the “low
pin5
20
F
3,50
3,00
2,50
2,00
1,50
1,00
0,50
0,00
REGUL
is then
”