NCP1631DR2G ON Semiconductor, NCP1631DR2G Datasheet - Page 15

• Manufacturer Part Number: NCP1631DR2G
• Description: IC CTLR PFC INTERLEAVED 16SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1631DR2G

• Mode: Critical Conduction (CRM), Discontinuous Conduction (DCM)
• Frequency - Switching: 130kHz
• Current - Startup: 100µA
• Voltage - Supply: 10 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

up−graded safety level as it protects the PFC stage even if
there is a failure of one of the two feed−back arrangements.
is possible as portrayed by Figure 14. The regulation and
OVP blocks having the same reference voltage, the
resistance ratio R
More specifically,
The bulk regulation voltage (“V
The OVP level (“V
The ratio OVP level over regulation level is:
(R
the OVP level, it maintains the power switch open to stop
the power delivery.
is “informed” when there is an OVP condition, not to
over−dimension V
OVP sequence would be viewed as a dead−time phase by
the circuit and V
compensate it (refer to Figure 7).
PfcOK / REF5V Signal
converter. The signal “pfcOK/REF5V” is high (5 V) when
the PFC stage is in normal operation (its output voltage is
stabilized at the nominal level) and low otherwise.
voltage is properly and safely regulated. “pfcOK/REF5V”
The double feed−back configuration offers some
However, if wished, one single feed−back arrangement
For instance, (V
When the circuit detects that the output voltage exceeds
As mentioned previously, the “V
The NCP1631 can communicate with the downstream
More specifically, “pfcOK/REF5V” is low:
Finally, “pfcOK/REF5V” is high when the PFC output
out3
− During the PFC stage start−up, that is, as long as
− Any time, the circuit is off or a fault condition is
V
V
V
V
out(nom)
out(ovp)
out(nom)
out(ovp)
= 5% x R
the output voltage has not yet stabilized at the
right level. The start−up phase is detected by
the latch “L
Figure 2. “L
phase so that its output (“STUP“) is high when
the circuit enters an active phase. The latch is
reset when the error amplifier stops charging
its output capacitor, that is, when the output
voltage of the PFC stage has reached its
desired regulation level. At that moment,
“STUP” falls down to indicate the end of the
start−up phase.
detected as described by the “Fault
management and OFF mode” section
+
+
+ 1 )
R
out2
R
out2
out1
TON
out1
out(nom)
TON
out(ovp)
).
R
over R
R
R
) R
) R
STUP
out2
STUP
out3
out2
would inappropriately increase to
in that conditions. Otherwise, an
R
”) is:
out2
out2
) R
out2
” of the block diagram in
= 105% x V
” is set during each “off”
out3
) R
) R
out3
adjusts the OVP threshold.
out(nom)
out3
TON
out3
@ V
@ V
processing circuit”
”) is:
out(nom)
ref
ref
) leads to:
(eq. 14)
(eq. 15)
(eq. 16)
http://onsemi.com
15
should be used to allow operation of the downstream
converter.
Oscillator Section – Phase Management
maximum switching frequency for the global system (f
In other words, each of the two interleaved branches cannot
operate above the clamp frequency that is half the oscillator
frequency (f
adjusted by the capacitor applied to pin 4. Typically, a
440 pF capacitor approximately leads to a 120−kHz
operating frequency, meaning a 60−kHz clamp frequency
for each branch. The oscillator frequency should be kept
below 500 kHz (which corresponds to a pin4 capacitor in
the range of 100 pF).
(35 mA typical) and I
pin 4 capacitor until its voltage exceeds V
typically). At that moment, the output of the COMP_OSC
comparator (“SYNC” of Figure 16) turns high and changes
the COMP_OSC reference threshold that drops from
V
enters a discharge phase where the I
disabled and instead a sink current I
typ.) discharges the pin 4 capacitor. This sequence lasts
until V
turns low and a new charging phase starts. A divider by two
uses the “SYNC” information to manage the phases of the
interleaved PFC: the first SYNC pulse sets “phase 1”, the
second one, “phase 2”, the third one phase 1 again... etc...
the relevant “Clock generator latch” that will generate the
clock signal (“CLK1” for phase 1, “CLK2” for phase 2)
when SYNC drops to zero (falling edge detector). So, the
drivers are synchronized to SYNC falling edge.
if the demagnetization of the coil is not yet complete (CrM
operation). In this case, the clock signal is maintained high
until the driver turns high (the clock generator latches are
reset by the corresponding driver is high − reset on rising
edge detector). Also, the discharge time can be prolonged
if when V
phase cannot turn on because the core is not reset yet (CrM
operation). In this case, V
turns high. The further discharge of V
helps maintain a substantial 180° phase shift in CrM that is
in essence, guaranteed in DCM. In the two conditions (CrM
or DCM), operation is stable and robust.
different cases:
OSC(high)
The oscillator generates the clock signal that dictates the
As shown by Figure 16, two current sources I
According to the selected phase, the “SYNC” signal sets
Actually, the drivers cannot turn on at this very moment
Figure 17 portrays the clock signal waveforms in
− In fixed frequency operation (DCM), the cycle
pin4
time of the coil current is shorter than an
oscillator period. Hence, as soon as the clock
signal goes high, the driver can turn on and
reset the clock generator latch. The clock
signal is then a short pulse.
pin4
goes below V
down to V
osc
drops below V
/2). The oscillator frequency (f
OSC(CH)
OSC(low)
OSC(low)
pin4
(105 mA typical) charge the
OSC(low)
decreases until the driver
(hysteresis). The system
when the “SYNC” signal
CH
pin4
OSC(DISCH)
, the driver of the
current source is
below V
OSC(high)
OSC(clamp)
(105 mA
OSC(low)
osc
(5 V
osc
) is
).