NCP1631DR2G ON Semiconductor, NCP1631DR2G Datasheet - Page 12

• Manufacturer Part Number: NCP1631DR2G
• Description: IC CTLR PFC INTERLEAVED 16SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1631DR2G

• Mode: Critical Conduction (CRM), Discontinuous Conduction (DCM)
• Frequency - Switching: 130kHz
• Current - Startup: 100µA
• Voltage - Supply: 10 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

variations of the load, may result in excessive over and
under−shoots. Over−shoots are limited by the Over−
Voltage Protection (see OVP section). To contain the
under−shoots, an internal comparator monitors the
feed−back signal (V
95.5% of its nominal value, it connects a 230 mA current
source to speed−up the charge of the compensation
capacitor (C
multiplied the error amplifier gain by 10.
limitation, is not enabled during the start−up sequence of
the PFC stage but only once the converter has stabilized
(that is when the “
high). This is because, at the beginning of operation, the
pin5 capacitor must charge slowly and gradually for a soft
start−up.
phase 1 and ZCD2 for phase 2), these pins are internally
clamped to about 0 V when the voltage applied by the
corresponding ZCD winding is negative. Similarly, the
ZCD pins are clamped to V
the ZCD voltage rises too high. Because of these clamps,
a resistor (R
current from the ZCD winding to the ZCD pin. The clamps
are designed to respectively source and sink 5 mA
minimum. It is recommended not to exceed this 5 mA level
within the ZCD clamps for a proper operation.
Negative
Provided the low bandwidth of the regulation loop, sharp
One must note that this circuitry for under−shoots
To prevent negative voltages on the ZCD pins (ZCD1 for
positive
clamp
1
and
ZCD2
pin5
ZCD
Negative
16
positive
clamp
). Finally, it is like if the comparator
and
of Figure 11) is necessary to limit the
pfcOK
ZCD1
pin2
) and when V
” signal of the block diagram, is
management
(from Fault
0.5 V
ZCD(high)
block)
0.5 V
OFF
+
−
+
−
200−ms
delay
Rzcd2
(10 V typical), when
Rzcd1
V
V
L
pin2
DMG1
DMG2
ZCD
Figure 11. Zero Current Detection
is lower than
Q
S
R
ZCD
S
R
Q
Q
http://onsemi.com
AND1
Qzcd1
Qzcd2
management
(from phase
block)
CLK2
management
12
(from phase
Vzcd2
block)
S
R
CLK1
Zero Current Detection
with the instantaneous input voltage. The NCP1631
determines the demagnetization completion by sensing the
inductor voltage, more specifically, by detecting when the
inductor voltage drops to zero.
configuration is taken off of the boost inductor and gives a
scaled down version of the inductor voltage that is usable
by the controller (Figure 12). In that way, the ZCD voltage
(“V
inductor current drops to zero. The NCP1631 detects this
falling edge and allows the next driver on time.
of the ZCD winding exceeds 0.5 V. When this is the case,
the coil is in demagnetization phase and the latch L
set. This latch is reset when the next driver pulse occurs.
protection that has tripped for instance), there is no energy
in the ZCD winding and therefore no voltage signal to
activate the ZCD comparator. This means that the driver
will never turn on. To avoid this, an internal watchdog
timer is integrated into the controller. If the driver remains
low for more than 200 ms (typical), the timer sets the L
latch as the ZCD winding signal would do. Obviously, this
200−ms delay acts as a minimum off−time if there is no
demagnetization winding while it has no action if there is
a ZCD voltage provided by the auxiliary winding.
Q
While the on time is constant, the core reset time varies
Practically,
Figure 1 shows how it is implemented.
For each phase, a comparator detects when the voltage
At startup or after an inactive period (because of a
AUX
(from PH2 PWM comparator)
Vzcd1
In−rush
SET2
DT
SET1
”) falls and starts to ring around zero volts when the
In−rush
latch PH2
PWM
(from PH1 PWM
S
R
PWM
latch
PH1
an
S
R
Q
Q
comparator)
reset signal
reset signal
auxiliary
buffe r 1
buffe r 2
Vcc
output
output
Vcc
Vin
Vin
DRV2
DRV1
winding
14
11
M2
L2
L1
M1
Cbulk
D1
D2 Vout
in
flyback
Cbulk
ZCD
ZCD
is