MCZ33999EK Freescale Semiconductor, MCZ33999EK Datasheet - Page 10

• Manufacturer Part Number: MCZ33999EK
• Description: IC SW 16OUTPT PWM & SPI 54-SOIC
• Manufacturer: Freescale Semiconductor
• Type: Low Sider

Specifications of MCZ33999EK

• Number Of Outputs: 16
• Rds (on): 550 mOhm
• Internal Switch(s): Yes
• Current Limit: 1.2A
• Voltage - Input: 5 ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

industrial applications. It is a 16-output power switch having
24-bit serial control. The 33999 incorporates SMARTMOS
technology having CMOS logic, bipolar / MOS analog
CHIP SELECT (CS)
communicated with through the use of the Chip Select (
pin. When the
transferred from the MCU to the 33999 and vise versa.
Clocked-in data from the MCU is transferred from the 33999
Shift register and latched into the power outputs on the rising
edge of the
output fault status information is transferred from the Power
Outputs Status register into the device’s SO Shift register.
The SO pin output driver is enabled when
information to be transferred from the 33999 to the MCU. To
avoid any spurious data, it is essential the high-to-low
transition of the
low state.
SYSTEM CLOCK (SCLK)
register of the 33999. The Serial Input (SI) pin accepts data
into the Input Shift register on the falling edge of the SCLK
signal while the Serial Output (SO) pin shifts data information
out of the Shift register on the rising edge of the SCLK signal.
False clocking of the Shift register must be avoided, ensuring
validity of data. It is essential the SCLK pin be in a logic low
state whenever the Chip Select (
transition. For this reason, it is recommended, though not
necessary, that the SCLK pin is commanded to a low logic
state as long as the device is not accessed (
state). When the
SCLK and SI pins is ignored and the SO is tri-stated (high
impedance).
SERIAL INPUT (SI)
serial instructions into the 33999. SI SPI bits are latched into
the Input Shift register on each falling edge of SCLK. The
Shift register is full after 24 bits of information are entered.
The 33999 operates on the command word on the rising edge
of
transition SI as the SCLK transitions from high-to-low state
(see
SERIAL OUTPUT (SO)
the 33999 to the MCU. The SO pin remains tri-state until the
10
33999
FUNCTIONAL DESCRIPTION
INTRODUCTION
CS
The 33999 is designed and developed for automotive and
The system MCU selects which 33999 is to be
The System Clock (SCLK) pin clocks the Internal Shift
The Serial Input (SI) pin is used to enter one of seven
The Serial Output (SO) pin transfers fault status data from
Figure
. To preserve data integrity, exercise care to not
CS
4, page 8).
CS
signal. On the falling edge of the
CS
CS
pin is in a logic low state, data can be
signal occur only when SCLK is in a logic
is in a logic high state, any signal at the
CS
) pin makes any
CS
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CS
is low, allowing
in logic high
CS
signal,
INTRODUCTION
CS
)
circuitry, and independent DMOS power output transistors.
Many benefits are realized as a direct result of using this
mixed technology.
internal block diagram of the 33999.
CS
are reported to the MCU as logic [1]. Conversely, normal
operating outputs with nonfaulted loads are reported as
logic [0]. On the falling edge of the
status information is transferred from the Power Outputs
Status register into the device’s SO Shift register. The first
eight positive transitions of SCLK will provide Any Fault (bit
23), Overvoltage Fault (bit 22), followed by six logic [0]s
(bits 21 to 16). The next 16 successive positive clock
provides fault status for output 15 to output 0. The SI / SO
shifting of data follows a first-in, first-out protocol with both
input and output words transferring the Most Significant Bit
(MSB) first.
SO OUTPUT DRIVER POWER SUPPLY (SOPWR)
output driver and Power-ON Reset (POR) circuit. To achieve
low standby current on VPWR supply, power must be
removed from the SOPWR pin. The 33999 will be in reset
with all drivers OFF when SO
does not detect overvoltage on the SOPWR supply pin.
OUTPUT/INPUT (OUT0 – OUT15)
load.
RESET
to turn OFF all outputs, thereby clearing all internal registers.
BATTERY INPUT (VPWR)
33999. The voltage on VPWR is monitored for overvoltage
protection and shutdown. An overvoltage condition (> 50 µs)
on the VPWR pin causes the 33999 to shut down all outputs
until the overvoltage condition is removed. Upon return to
normal input voltage, the outputs respond as programmed by
the overvoltage bit in the Global Shutdown/Retry Control
register. The overvoltage threshold on the VPWR pin is
specified as 27.5 V to 35 V with 1.4 V typical hysteresis.
Following an overvoltage shutdown of output drivers, the
Overvoltage Fault and the Any Fault bits in the SO bit stream
will be logic [1].
The SOPWR pin is used to supply power to the 33999 SO
These pins are low-side output switches controlling the
The Reset (
The VPWR pin is used as the input power source for the
pin transitions to a logic low state. All faults on the 33999
(RST)
RST
) pin is the active low reset input pin used
Figure 2,
Analog Integrated Circuit Device Data
page
PWR
is below 2.5 V. The 33999
2,
Freescale Semiconductor
CS
illustrates a simplified
signal, output fault