MCZ33999EK Freescale Semiconductor, MCZ33999EK Datasheet - Page 16

• Manufacturer Part Number: MCZ33999EK
• Description: IC SW 16OUTPT PWM & SPI 54-SOIC
• Manufacturer: Freescale Semiconductor
• Type: Low Sider

Specifications of MCZ33999EK

• Number Of Outputs: 16
• Rds (on): 550 mOhm
• Internal Switch(s): Yes
• Current Limit: 1.2A
• Voltage - Input: 5 ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWM ENABLE REGISTER
PWM controlled. The first 8 bits of the 24 bit SPI message
word are used to identify the
remaining 16 bits are used to enable or disable the PWM of
the output drivers.
OR / AND the PWM input with SPI Control bit and disables the
specific parallel control input (PWM0, PWM1, PWM6, PWM7,
PWM8, PWM9, PWM14, and PWM15).
PWM to a specific output and allow the user to use the
parallel PWM control inputs (PWM0, PWM1, PWM6, PWM7,
PWM8, PWM9, PWM14, and PWM15) and the SPI ON /OFF
Control bits. Power-ON Reset (POR) or the
RESET command will set the PWM enable register to
logic[0].
AND /OR Control Register
which the PWM pin controls the output driver. A logic [0] in
the AND / OR Control register will AND the PWM pin with the
control bit in the SPI Control register. Likewise, a logic [1] in
the AND / OR Control register will OR the PWM pin with the
control bit in the ON/OFF Control register (see
16
33999
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
On/Off Control Bit
PWM IN
AND/OR Control Bit
On/Off control Bit
PWM IN
The PWM Enable register determines the outputs that are
A logic [1] in the PWM Enable register allows the user to
A logic [0] in the PWM Enable register will disable the
The AND /OR Control register describes the condition by
Figure 13. PWM Control Logic Diagram
On/Off Control Bit
PWM Enable Bit
PWM
enable command, and the
RST
Figure
pin or the
13).
To Gate
Control
SERIAL OUTPUT (SO) RESPONSE REGISTER
All logic [1]s received by the MCU via the SO pin indicate
fault. All logic [0]s received by the MCU via the SO pin
indicate no fault. All fault bits are cleared on the positive edge
of
to 0. SO bits 21 to 16 will always return logic [0]. Bit 22
provides overvoltage condition status, and bit 23 is set when
any fault is present in the IC. The timing between two write
words must be greater than 450 µs to allow adequate time to
sense and report the proper fault status.
RESET COMMAND
internal registers to their Power-ON Reset state (refer to
Table
FAULT OPERATION
sent to the 33999 and a 24-bit fault word is received from the
33999.
CS
Fault reporting is accomplished through the SPI interface.
The RESET command turns all outputs OFF and sets all
On each SPI communication, a 24-bit command word is
The Most Significant Bit (MSB) is sent and received first.
Command Register Definition:
SO Definition:
. SO bits 15 to 0 represent the fault status of outputs 15
5).
0 = Output Command Off
1 = Output Command On
0 = No fault
1 = Fault
Analog Integrated Circuit Device Data
Freescale Semiconductor