ISL6441IRZ Intersil, ISL6441IRZ Datasheet
ISL6441IRZ
Specifications of ISL6441IRZ
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ISL6441IRZ Summary of contents
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... PART RANGE (Note) MARKING (°C) ISL6441IRZ* ISL 6441IRZ - QFN *Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach ...
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Pinout 2 ISL6441 ISL6441 (28 LD QFN) TOP VIEW PHASE2 1 ISEN2 2 PGOOD 3 VCC_5V 4 5 SD2 6 SS2 7 OCSET2 ISEN1 21 PGND 20 ...
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Block Diagram BOOT1 UGATE1 PHASE1 ADAPTIVE DEAD-TIME DIODE EMULATION VCC_5V V/I SAMPLE TIMING LGATE1 PGND 0.8V REFERENCE + GATE3 + FB3 18.5pF 800kΩ 180kΩ FB1 - 16kΩ 0.8V ERROR AMP 1 ...
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... R7 PHASE2 1 22 PHASE1 1.5k ISEN2 2 21 ISEN1 LGATE2 26 25 LGATE1 FB2 8 20 PGND SGND 9 15 FB1 SD2 5 14 SGND 29 SGND U1 ISL6441IRZ SD1 R10 120k 0.01µF 0.01µF 120k C5 0.1uF Q2A C21 L2 3.3µH 10µF R9 1.5k Q2B C30 C8 150µF FDS6990S ...
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... Maximum Junction Temperature (Plastic Package) -55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = 5.6V to 24V, or VCC_5V = 5V ±10 +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical Application Schematic” on page 4. V values are at T specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical Application Schematic” on page 4. V values are at T specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER ...
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Typical Performance Curves 3.40 3.39 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.30 0 0.5 1.0 1.5 2.0 2.5 LOAD CURRENT (A) FIGURE 1. PWM1 LOAD REGULATION 0.85 0.84 0.83 0.82 0.81 0.80 0.79 0.78 0.77 0.76 0.75 -40 ...
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Typical Performance Curves V 200mV/DIV OUT1 AC COUPLED I 1A/DIV OUT1 FIGURE 7. LOAD TRANSIENT RESPONSE V VCC_5V 1V/DIV V 1V/DIV OUT1 FIGURE 9. PWM SOFT-START WAVEFORM 100 0.5 1.0 1.5 2.0 2.5 LOAD CURRENT (A) ...
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Pin Descriptions BOOT2, BOOT1 - These pins power the upper MOSFET drivers of each PWM converter. Connect this pin to the junction of the bootstrap capacitor (CBOOT) and the cathode of the bootstrap diode. The anode of the bootstrap diode ...
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The internal LDO can source over 60mA to supply the IC, power the low side gate drivers, charge the external boot capacitor and supply small external loads. When driving large FETs especially at 1.4MHz frequency, little or no regulator current ...
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EMI. The typical operating curves show the ° synchronized 180 out-of-phase operation. Input Voltage Range The ISL6441 is designed to operate from input supplies ranging from 4.5V to 24V. However, the input voltage range can be effectively limited ...
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IC enters a hiccup mode by turning off the gate drivers and entering into soft-start. The IC will cycle 2x through soft-start before trying to restart. The IC will continue to ...
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Due to the current loop feedback, the modulator has a single pole response with -20 slope at a frequency determined dB by the load as shown in Equation -------------------------------- - = ⋅ ⋅ PO 2π ...
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FEEDBACK VOLTAGE (V) FIGURE 21. LINEAR CONTROLLER GAIN Base-Drive Noise Reduction The high-impedance base driver is susceptible to system noise, especially when the linear regulator is lightly loaded. Capacitively ...
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The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle (see Equations 10 and 11). The conduction losses are the main component of power ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/07 5.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 4. 65 TYP ) ( 3. 10) TYPICAL RECOMMENDED LAND PATTERN 18 ISL6441 A B ...