L9952XP STMicroelectronics, L9952XP Datasheet - Page 54

• Manufacturer Part Number: L9952XP
• Description: IC PWR MANAGEMENT SYST PWRSSO36
• Manufacturer: STMicroelectronics

Specifications of L9952XP

• Applications: Automotive
• Voltage - Supply: 6 V ~ 18 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: PowerSSO-36 Exposed Bottom Pad
• Product: Fan / Motor Controllers / Drivers
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SPI control and status registers
8
8.1
Table 35.
Note:
54/68
D23
A1
Err
Err
Register 0
Register 1
Register 2
Register 0
Register 1
0
0
1
Address
Control
Control
Control
Status
Status
[write]
[write]
[write]
[read]
D22
Err
Err
A0
0
1
0
CLR INT_en
RES
RES
D21
VCC
RES
GO
Reserved
Reserved
SPI control and status registers
SPI registers
24bit shift register: first 2 bits are address (A1,A0) and 22 bits are data.
During power-on reset, all registers are set to zero.
SPI registers
During the shift in of the address bits, (2 clock periods) an internal error bit (Err) is fed to the
DO output.
D23,D22 -> error flags (seen from DO)
The error flag is generated by logic OR combination of following error bits:
VCC_Fail1,2; TSD1,2; TW; OV,UW; OC_HS1..4; OC_OUTHS; OC_REL1..2; OC_V2
RES
D20
V
I
RES
GO
CMP
BAT
TRIG
Timer
COLD
START
OVUV
DOM
TXD
D19
T20
LS
2
LIN State
Wakeup
D18
V21
Slope
SHT
BAT
T13
L I N
ON
LIN
On5V2
GND
D17
SHT
V20
T12
I NH
ON
IC
41
Timer
1
TRIG
WU4
REL
D16
T11
40
IC
2
Wakeup input status
WU3
REL
D15
T10
WD
31
IC
1
3
Watchdog Reset
Input config
OUT
WU2 WU1
HS2
D14
WD
L2
30
IC
2
Doc ID 13518 Rev 5
OUT
D13
HS1
Loop
WD
L1
21
IC
1
SHT5
OUT
HS0
D12
WD
V2
L0
IC
20
0
Address
Address
Address
Address
Address
D11
Rel2
OC
HS
U3
R2
42
11
IC
Data
5V Restarts
Pullup / down
Rel1
D10
HS
OC
U2
R1
41
10
IC
Reset level
LEV
D09
Overcurrent
OC
HS
HS
U1
R0
40
1
On Signals
D08
LEV
HS4
ST1
OC
HS
U0
32
0
State
TOUT
HS3
D07
TXT
ST0
HS
W7
OC
31
Wakeup Sources OL
LIN
LINPU
VCC
D06
HS2
W6
OC
Fail
HS
30
2
O_HS
VCC
HS1
D05
REC
Fail
HS
W5
OC
22
1
VLOCK
TSD
D04
OUT
W4
HS
HS
OL
21
2
HS4
HS4
TSD
D03
OLT
W3
HS
OL
20
1
Openload treshold
Openload
Wakeup Sources
D02
OLT
HS3
HS3
L9952GXP
W2
TW
HS
OL
12
HS2
HS2
D01
OLT
HS
W1
UV
OL
11
HS1
HS1
D00
OLT
HS
W0
OL
OV
10