LP3927ILQ-AZ/NOPB National Semiconductor, LP3927ILQ-AZ/NOPB Datasheet - Page 4

• Manufacturer Part Number: LP3927ILQ-AZ/NOPB
• Description: IC PWR MNGMNT CELL/PCS 28-LLP
• Manufacturer: National Semiconductor

Specifications of LP3927ILQ-AZ/NOPB

• Applications: Handheld/Mobile Devices
• Current - Supply: 5µA
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LP3927ILQ-AZ

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Pin Descriptions
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
OP_AMP_OUT Operational amplifier output pin.
OP_AMP_V
TEST_MODE
LED_PGM
PS_HOLD
A_GND2
A_GND1
LED_EN
D_GND
Name
KYBD
VEXT
V
V
V
VO1
RST
BYP
VO5
VO4
VO3
VO2
EN5
EN4
EN3
LED
IRQ
IN−
IN+
DD3
DD2
DD1
DD
150 mA, LDO1 output pin.
LDO5 enable input.
LDO4 enable input.
LDO3 enable input.
Externally pulled high, open drain output to processor/memory reset.
Externally pulled high, open drain output to processor interrupt indicating KYBD has gone
high.
Input from the processor to the LP3927. A HIGH indicates a steady supply of power is
granted. Refer to "Application Hints" section for more detail.
An active high input signal indicating the keyboard “On/Off” button has been asserted. Refer
to "Application Hints" section for more detail.
Digital ground, used primarily for the digital and DAC circuits.
Active low input indicating a battery charger insertion Refer to "Application Hints" section for
more detail.
Reference bypass pin.
Pin used for production testing, factory use only. This pin should be grounded in applications.
LED driver enable input.
LED driver, drain connection of the LED drive MOSFET.
LED drive current programming pin.
− input of the Op-Amp.
+ input of the Op-Amp.
Power supply pin for Op-Amp.
Ground for analog.
200 mA, LDO5 output pin.
Input power pin for LDO5. V
150 mA, LDO4 output pin.
Input power pin for LDO3 and LDO4. V
100 mA, LDO3 output pin.
Ground for analog.
200 mA, LDO2 output pin.
Input power pin for LDO1 and LDO2. V
DD1
, V
4
DD2
Functional Description
and V
DD1
DD1
, V
, V
DD3
DD2
DD2
must be tied together externally.
and V
and V
DD3
DD3
must be tied together externally.
must be tied together externally.