LM96163CISD/NOPB National Semiconductor, LM96163CISD/NOPB Datasheet - Page 38

• Manufacturer Part Number: LM96163CISD/NOPB
• Description: IC TEMP SENSOR DGTL REMOTE 10LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96163CISD/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Register Bank, Tach
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-LLP
• Temperature Sensor Function: Temp Sensor
• Interface Type: Serial (2-Wire)
• Resolution: 10+SignBit
• Package Type: LLP EP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96163CISDTR

www.national.com
3.4.2 Calculating Total System Accuracy
The voltage seen by the LM96163 also includes the I
age drop of the series resistance. The non-ideality factor, η,
is the only other parameter not accounted for and depends
on the diode that is used for measurement. Since ΔV
proportional to both η and T, the variations in η cannot be
distinguished from variations in temperature. Since the non-
ideality factor is not controlled by the temperature sensor, it
will directly add to the inaccuracy of the sensor. For the for
Intel processor on 65nm process, Intel specifies a +4.06%/
−0.897% variation in η from part to part when the processor
diode is measured by a circuit that assumes diode equation,
Equation
sensor has an accuracy specification of ±1.0°C at a temper-
ature of 80°C (353 Kelvin) and the processor diode has a non-
ideality variation of +4.06%/−0.89%. The resulting system
accuracy of the processor temperature being sensed will be:
and
TruTherm technology uses the transistor equation,
4, resulting in a non-ideality spread that truly reflects the pro-
cess variation which is very small. The transistor equation
non-ideality spread is ±0.39% for the 65nm thermal diode.
The resulting accuracy when using TruTherm technology im-
proves to:
Intel does not specify the diode model ideality and series re-
sistance of the thermal diodes on 45nm so a similar compar-
ison cannot be calculated, but lab experiments have shown
similar improvement. For the 45nm processor the ideality
spread as specified by Intel is -0.399% to +0.699%. The re-
sulting spread in accuracy when using TruTherm technology
with the thermal diode on Intel processors with 45nm process
is:
to
The next error term to be discussed is that due to the series
resistance of the thermal diode and printed circuit board
traces. The thermal diode series resistance is specified on
most processor data sheets. For Intel processors in 45 nm
process, this is specified at 4.5Ω typical with a minimum of
3Ω and a maximum of 7Ω. The LM96163 accommodates the
typical series resistance of Intel Processor on 45 nm process.
The error that is not accounted for is the spread of the
processor's series resistance. The equation used to calculate
the temperature error due to series resistance (T
LM96163 is simply:
Solving
the additional error due to the spread in this series resistance
of -0.93°C to +1.55°C. The spread in error cannot be canceled
out, as it would require measuring each individual thermal
diode device. This is quite difficult and impractical in a large
volume production environment.
Equation 6
caused by series resistance on the printed circuit board. Since
the variation of the PCB series resistance is minimal, the bulk
of the error term is always positive and can simply be can-
T
T
T
ACC
T
ACC
T
ACC
Equation 6
ACC
ACC
4, as true. As an example, assume a temperature
= +0.75°C + (+0.799% of 353 K) = +4.32 °C
= ±0.75°C + (±0.39% of 353 K) = ± 2.16 °C
can also be used to calculate the additional error
= + 1.0°C + (+4.06% of 353 K) = +15.3 °C
= -0.75°C + (-0.39% of 353 K) = -2.16 °C
= - 1.0°C + (−0.89% of 353 K) = −4.1 °C
for R
PCB
equal to -1.5Ω to 2.5Ω results in
ER
Equation
F
) for the
R
S
BE
volt-
(6)
is
38
celled out by subtracting it from the output readings of the
LM96163 using the Remote Temperature Offset register.
3.5 PCB LAYOUT FOR MINIMIZING NOISE
In a noisy environment, such as a processor mother board,
layout considerations are very critical. Noise induced on
traces running between the remote temperature diode sensor
and the LM96163 can cause temperature conversion errors.
Keep in mind that the signal level the LM96163 is trying to
measure is in microvolts. The following guidelines should be
followed:
1.
2.
3.
4.
Processor Family
Intel Processor on
45 nm process
Intel Processor on
65 nm process
Use a low-noise +3.3VDC power supply, and bypass to
GND with a 0.1 µF ceramic capacitor in parallel with a
100 pF ceramic capacitor. The 100 pF capacitor should
be placed as close as possible to the power supply pin.
A bulk capacitance of 10 µF needs to be in the vicinity of
the LM96163's V
A 100 pF diode bypass capacitor is recommended to filter
high frequency noise but may not be necessary. Place
the recommended 100 pF diode capacitor as close as
possible to the LM96163's D+ and D− pins. Make sure
the traces to the 100 pF capacitor are matched. The
LM96163 can handle capacitance up to 3 nF placed
between the D+ and D- pins, See Typical Performance
Characteristic curves titled Remote Temperature
Reading Sensitivity to Thermal Diode Filter
Capacitance.
Ideally, the LM96163 should be placed within 10 cm of
the Processor diode pins with the traces being as
straight, short and identical as possible. Trace resistance
of 1 Ω can cause as much as 0.62°C of error. This error
can be compensated by using the Remote Temperature
Offset Registers, since the value placed in these
registers will automatically be subtracted from or added
to the remote temperature reading.
Diode traces should be surrounded by a GND guard ring
to either side, above and below if possible. This GND
guard should not be between the D+ and D− lines. In the
event that noise does couple to the diode lines it would
be ideal if it is coupled common mode. That is equally to
the D+ and D− lines.
FIGURE 9. Ideal Diode Trace Layout
DD
pin.
0.997
0.997
Transistor Equation η
min
non-ideality
1.001
1.001
typ
1.008
1.005
max
T
,
Series
30041021
4.52
R,Ω
4.5