ISL6431CB Intersil, ISL6431CB Datasheet - Page 6

• Manufacturer Part Number: ISL6431CB
• Description: IC CNTRLR PWM SYNC BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6431CB

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 340kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 340kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors C
represent numerous physical capacitors. Locate the ISL6431
within 3 inches of the MOSFETs, Q
for the MOSFETs’ gate and source connections from the
ISL6431 must be sized to handle up to 1A peak current.
Figure 4 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
the COMP/OCSET pin and locate the resistor, R
to the COMP/OCSET pin because the internal current source
is only 20 A. Provide local V
GND pins. Locate the capacitor, C
to the BOOT and PHASE pins. All components used for
feedback compensation should be located as close to the IC a
practical.
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
error amplifier (Error Amp) output (V
the oscillator (OSC) triangular wave to provide a pulse-
+5V
OUT
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
ISL6431
) is regulated to the Reference voltage level. The
COMP/OCSET
ISL6431
UGATE
PHASE
LGATE
GND
GROUND PLANES OR ISLANDS
LAYOUT GUIDELINES
BOOT
PHASE
VCC
C
BOOT
Q
Q
+5V
V
RETURN
CC
IN
2
1
6
C
decoupling between VCC and
D
VCC
IN
1
1
BOOT
and C
and Q
E/A
C
as close as practical
O
) is compared with
Q
IN
2
+V
Q
1
may each
. The circuit traces
2
L
IN
O
L
C
O
O
OSCET
C
O
V
OUT
close
V
OUT
ISL6431
width modulated (PWM) wave with an amplitude of V
the PHASE node. The PWM wave is smoothed by the output
filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage V
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6431) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
F
1. Pick Gain (R
2. Place 1
3. Place 2
4. Place 1
5. Place 2
3
LC
V
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
OSC
, C
=
FB
1
----------------------------------------- -
2 x
O
, C
. The goal of the compensation network is to provide
and C
OSC
2
ST
, and C
ND
ST
ND
0dB
COMPARATOR
OUT
L
1
COMPENSATION DESIGN
O
ERROR
AMP
Zero Below Filter’s Double Pole (~75% F
O
DETAILED COMPENSATION COMPONENTS
Pole at the ESR Zero.
V
Zero at Filter’s Double Pole.
Pole at Half the Switching Frequency.
ISL6431
) and adequate phase margin. Phase margin
E/A
x C
).
2
PWM
/V
/R
3
Z
E/A
+
O
-
) in Figure 7. Use these guidelines for
1
-
+
FB
COMP
LC
) for desired converter bandwidth.
C
. This function is dominated by a DC
REFERENCE
1
REFERENCE
and a zero at F
C
+
2
-
O
DRIVER
DRIVER
R
F
and C
Z
2
ESR
IN
OSC
=
FB
O
Z
------------------------------------------ -
2 x ESR x C
FB
), with a double pole
ESR
.
PHASE
V
(PARASITIC)
C
IN
3
IN
L
Z
R
. The DC Gain of
1
IN
O
1
) divided by the
R
ESR
3
C
O
V
OUT
O
0dB
V
LC
1
IN
OUT
, R
and
IN
).
at
2
,