L6725TR STMicroelectronics, L6725TR Datasheet - Page 13

• Manufacturer Part Number: L6725TR
• Description: IC CTRLR PWM ADJ STP DWN 16SOICN
• Manufacturer: STMicroelectronics

Specifications of L6725TR

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 550kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 18 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 550kHz
• Output Voltage: 0.6 V to 18 V
• Output Current: 30 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• For Use With: 497-5867 - EVAL BOARD 20A 250KHZ L6725497-5500 - EVAL BOARD FOR L6725
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5096-2

L6725 - L6725A
Figure 6.
Figure 7.
L6725:The output of the error amplifier is clamped with this voltage (VSS) until it reaches the
programmed value.
L6725A:The reference of the error amplifier is clamped with this voltage (VSS) until it reaches
the programmed value. No switching activity is observable if V
MOSFETs are OFF. When V
As V
MOSFET begins to switch and the output voltage starts to increase. During the soft-start phase
the current can’t be reversed in order to allow pre-biased start-up (see
If an over current is detected during the soft-start phase, the device provides a constant-
current-protection. In this way, in case of short soft-start time and/or small inductor value and/or
high output capacitors value, the converter can start in any case, limiting the current
(Chapter 5.8: Monitoring and protections on page
reaches 3.5V. After that the over-current-protection triggers the HICCUP mode.
Start-up without pre-bias
Start-up with pre-bias
SS
reaches 1.1V (i.e. the oscillator triangular wave inferior limit) even the high-side
SS
is between 0.5V and 1.1V the low-side MOSFET is turned ON.
14). The soft-start phase ends when Vss
SS
is lower than 0.5V and both
LGate
V
Figure 6.
V
I
SS
V
LGate
OUT
L
V
OUT
SS
I
L
Device description
and
Figure
13/32
7.).