ISL6545ACBZ-TS2698 Intersil, ISL6545ACBZ-TS2698 Datasheet - Page 11

• Manufacturer Part Number: ISL6545ACBZ-TS2698
• Description: IC PWM BUCK BST VM 8SOIC
• Manufacturer: Intersil

Specifications of ISL6545ACBZ-TS2698

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 660kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 14.4 V
• Buck: Yes
• Boost: Yes
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 660kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The modulator transfer function is the small-signal transfer
function of V
gain, given by d
filter, with a double pole break frequency at F
F
channel inductance and its DCR, while C and E represent the
total output capacitance and its equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6545x) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 9. Use the following guidelines for locating the
poles and zeros of the compensation network:
F
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
CE
LC
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
value for R2 for desired converter bandwidth (F
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 9, the design procedure can
be followed as presented.
=
. For the purpose of this analysis, L and D represent the
CIRCUIT
---------------------------
2π
PWM
⋅
1
L C
COMP
OUT
0
⋅
; typically 0.1 to 0.3 of F
COMPENSATION DESIGN
MAX
/V
HALF-BRIDGE
OSCILLATOR
COMP
V
OSC
V
E/A
DRIVE
IN
R2
ISL6545x
/V
. This function is dominated by a DC
C2
OSC
+
F
-
VREF
CE
C1
11
, and shaped by the output
=
----------------------- -
2π C E
FB
UGATE
LGATE
PHASE
EXTERNAL CIRCUIT
0dB
⋅
SW
1
⋅
and 180°. The
R3
Ro
) and adequate phase
V
IN
R1
LC
C3
L
and a zero at
V
0
D
ISL6545, ISL6545A
OUT
). If
C
E
(EQ. 3)
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The equations shown in Equations 8
and 9 describe the frequency response of the modulator
(G
response (G
G
COMPENSATION BREAK FREQUENCY EQUATIONS
G
G
F
F
2. Calculate C1 such that F
3. Calculate C2 such that F
4. Calculate R3 such that F
Z1
Z2
MOD
FB
CL
MOD
C2
R3
R2
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
C1
such that F
times F
Change the numerical factor to reflect desired placement
of this pole. Placement of F
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
f ( )
f ( )
=
=
f ( )
------------------------------- -
2π R2 C1
-------------------------------------------------- -
2π
), feedback compensation (G
=
=
=
=
=
=
⋅
=
----------------------------------------------- -
2π R2 0.5 F
---------------------------------------------------------
2π R2 C1 F
--------------------- -
F
----------- - 1
----------------------------------------------------- - ⋅
s f ( ) R1
---------------------------------------------------------------------------------------------------------------------------- -
(
-------------------------------------------- -
d
G
⋅
⋅
F
1
V
(
MAX
SW
SW
LC
1
MOD
d
----------------------------- -
R1
1
R1
+
OSC
⋅
CL
⋅
MAX
+
⋅
s f ( ) R3 C3
V
⋅
P2
). F
–
s f ( ) R2 C1
+
):
1
OSC
⋅
f ( ) G
R3
⋅
V
⋅
⋅
1
⋅
is placed below F
⋅
R1 F
⋅
IN
C1
SW
V
⋅
⋅
(
) C3
C1
IN
1
⋅
⋅
LC
⋅
⋅
⋅
FB
F
+
⋅
represents the switching frequency.
⋅
⋅
LC
+
s f ( )
0
----------------------------------------------------------------------------------------
1
LC
CE
(to adjust, change the 0.5 factor to
f ( )
C2
+
F
)
C3
P1
–
s f ( )
⋅
Z1
⋅
)
P1
Z2
1
(
⎛
⎝
R1
1
=
=
is placed at a fraction of the F
is placed at F
is placed at F
⋅
+
F
P2
(
---------------------------------------------- -
2π R2
-------------------------------------------------
2π R3 0.7 F
P2
1
+
s f ( ) R2
E
where s f ( )
+
R3
+
SW
lower in frequency helps
⋅
⋅
CE
=
s f ( ) E C
D
⋅
FB
) C3
) C
------------------------------- -
2π R3 C3
/F
⋅
(typically, 0.5 to 1.0
⋅
⋅
⋅
) and closed-loop
⋅
1
,
1
LC
--------------------- -
C1
⋅
C1 C2
⋅
⎛
⎝
+
⋅
--------------------- -
C1
1
, the lower the F
C1 C2
CE
LC
LC
s
+
⋅
⋅
2
⋅
=
C2
f ( ) L C
+
. Calculate C3
SW
).
⋅
.
2π f j
C2
⋅
⎞
⎠
⋅ ⋅
⋅
⎞
⎠
March 3, 2011
FN6305.6
(EQ. 4)
(EQ. 5)
(EQ. 6)
(EQ. 7)
(EQ. 9)
(EQ. 8)
LC
Z1
,