ISL6535IRZ-TK Intersil, ISL6535IRZ-TK Datasheet - Page 10

• Manufacturer Part Number: ISL6535IRZ-TK
• Description: IC CTRLR PWM SYNC BUCK 16-QFN
• Manufacturer: Intersil

Specifications of ISL6535IRZ-TK

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 8 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previously mentioned guidelines
should yield a compensation gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
capabilities of the error amplifier. The closed loop gain, G
constructed on the log-log graph of Figure 8 by adding the
modulator gain, G
compensation gain, G
G
F
F
4. Calculate R
3. Calculate C
Z1
Z2
MOD
G
G
FB
CL
C
C
such that F
times f
regulator. Change the numerical factor (0.7) below to
reflect desired placement of this pole. Placement of F
lower in frequency helps reduce the gain of the
compensation network at high frequency, in turn reducing
the HF ripple component at the COMP pin and minimizing
resultant duty cycle jitter.
R
C
=
=
1
2
3
3
f ( )
f ( )
f ( )
------------------------------ -
2π R
-------------------------------------------------
2π
=
=
=
=
=
=
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
------------------- -
---------------------------------------------- -
2π R
=
f
---------- - 1
F
⋅
⋅
SW
SW
(
LC
1
R
D
------------------------------ -
--------------------------------------------------- - ⋅
s f ( ) R
------------------------------------------------------------------------------------------------------------------------ -
(
G
R
2
1
⋅
⋅
⋅
1
1
1
MAX
MOD
). f
⋅
–
+
V
1
+
P2
+
C
2
2
2
3
3
OSC
⋅
s f ( ) R
SW
1
R
s f ( ) R
⋅
⋅
⋅
such that F
such that F
1
1
FB
0.5 F
C
0.7 f
⋅
f ( ) G
3
C
is placed below f
MOD
1
V
) C
1
1
⋅
⋅
) and closed-loop response (G
represents the switching frequency of the
⋅
IN
⋅
(
⋅
⋅
⋅
⋅
C
F
1
FB
3
SW
3
⋅
CE
2
1
LC
+
FB
(in dB), to the feedback
⋅
---------------------------------------------------------------------------------------------------------- -
1
⋅
+
C
s f ( )
(in dB). This is equivalent to
C
+
f ( )
–
C
3
1
s f ( )
)
P1
1
2
Z2
F
F
⋅
)
⋅
10
P1
P2
⎛
⎜
⎝
(
1
is placed at F
R
is placed at F
⋅
(
1
+
=
=
ESR
+
where s f ( )
s f ( ) R
1
SW
-------------------------------------------- -
2π R
------------------------------ -
2π R
R
+
3
s f ( ) ESR C
⋅
+
⋅
⋅
) C
(typically, 0.3 to 1.0
P2
⋅
DCR
1
,
MOD
2
2
3
against the
⋅
⋅
3
⋅
⋅
1
⎛
⎜
⎝
-------------------- -
C
C
C
CE
-------------------- -
C
LC
C
) C
1
3
1
), feedback
=
1
⋅
1
+
.
⋅
. Calculate C
+
⋅
2π f j
C
⋅
C
C
C
+
2
2
2
2
s
⋅ ⋅
CL
⎞
⎟
⎠
2
⎞
⎟
⎠
f ( ) L C
(EQ. 10)
(EQ. 14)
(EQ. 12)
(EQ. 13)
(EQ. 11)
):
CL
⋅
P2
, is
⋅
3
ISL6535
multiplying the modulator transfer function and the
compensation transfer function and then plotting the
resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, f
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor’s ESR will determine the output ripple
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
0
LOG
20
log
⎛
⎝
R2
------- -
R1
⎞
⎠
F
Z1
F
F
LC
Z2
SW
.
F
F
CE
P1
F
0
F
20
P2
log
G
CL
COMPENSATION GAIN
D MAX V
--------------------------------- -
OPEN LOOP E/A GAIN
CLOSED LOOP GAIN
G
V OSC
MODULATOR GAIN
MOD
FREQUENCY
⋅
IN
G
May 5, 2008
FB
FN9255.1