HIP6004ECBZ-T Intersil, HIP6004ECBZ-T Datasheet - Page 7

• Manufacturer Part Number: HIP6004ECBZ-T
• Description: IC CTRLR PWM VOLTAGE MON 20-SOIC
• Manufacturer: Intersil

Specifications of HIP6004ECBZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 100%
• Voltage - Supply: 5 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE: 0 = connected to GND or V
VID pins to HIGH.
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
Please note that the capacitors C
numerous physical capacitors. Locate the HIP6004E within 3
inches of the MOSFETs, Q
MOSFETs’ gate and source connections from the HIP6004E
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS pin and locate the capacitor, C
close to the SS pin because the internal current source is
only 10µA. Provide local V
GND pins. Locate the capacitor, C
to the BOOT and PHASE pins.
VID25
mV
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
0
1
0
1
0
1
HIP6004E
VID3
UGATE
PHASE
LGATE
PGND
1
1
1
1
1
1
GROUND PLANES OR ISLANDS
PIN NAME
VID2
1
1
1
1
1
1
1
CC
Q
V
Q
RETURN
and Q
VID1
2
IN
1
1
1
1
1
0
0
decoupling between VCC and
7
SS
IN
, 1 = connected to V
D
2
BOOT
2
and C
. The circuit traces for the
VID0
1
1
0
0
1
1
TABLE 1. OUTPUT VOLTAGE PROGRAM (Continued)
C
as close as practical
O
IN
each represent
L
O
VOLTAGE DACOUT
NOMINAL OUTPUT
C
O
V
OUT
DD
1.300
1.325
1.350
1.375
1.400
1.425
through pull-up resistors or leave the pins floating. Internal pull-ups will force the floating
SS
HIP6004E
VID25
mV
0
1
0
1
0
1
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
error amplifier (Error Amp) output (V
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V
the PHASE node.
C
OUT
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
SS
SS
VID3
) is regulated to the Reference voltage level. The
0
0
0
0
0
0
HIP6004E
PIN NAME
GND
LAYOUT GUIDELINES
VID2
1
1
1
1
1
1
BOOT
PHASE
VCC
C
BOOT
VID1
1
1
1
1
0
0
+12V
C
D
VCC
VID0
1
1
1
0
0
1
1
E/A
VOLTAGE DACOUT
) is compared with
NOMINAL OUTPUT
Q
Q
+V
1
2
IN
L
O
1.700
1.725
1.750
1.775
1.800
1.825
C
O
IN
V
OUT
at