ISL6535CBZ Intersil, ISL6535CBZ Datasheet - Page 8

• Manufacturer Part Number: ISL6535CBZ
• Description: IC CTRLR SYNC BUCK PWM 14-SOIC
• Manufacturer: Intersil

Specifications of ISL6535CBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The OCP trip point varies mainly due to MOSFET r
variations and layout noise concerns. To avoid overcurrent
tripping in the normal operating load range, find the R
resistor from the following equations with:
Determine the overcurrent trip point greater than the
maximum output continuous current at maximum inductor
ripple current.
High Speed MOSFET Gate Driver
The integrated driver has the same drive capability and
feature as the Intersil’s 12V gate driver, ISL6612. The PWM
tri-state feature helps prevent a negative transient on the
output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some systems
for protecting the microprocessor from reversed-output-
voltage damage. See the ISL6612 datasheet FN9153 for
specification parameters that are not defined in the current
ISL6535 “Electrical Specifications” table on page 4.
Reference Input
The REFIN pin allows the user to bypass the internal 0.597V
reference with an external reference. If REFIN is NOT above
~2.2V, the external reference pin is used as the control
reference instead of the internal 0.597V reference. When not
using the external reference option, the REFIN pin should be
left floating. An internal 6
above 2.2V in this situation.
Internal Reference and System Accuracy
The Internal Reference is set to 0.597V. The total DC system
accuracy of the system is to be within 1.0% over commercial
temperature range and 1.5% over the industrial temperature
range. System Accuracy includes Error Amplifier offset, and
Reference Error. The use of REFIN may add up to 3mV of
offset error into the system (as the Error Amplifier offset is
trimmed out via the internal System reference).
1. The maximum r
2. The minimum I
temperature
N
R
ΔI =
U
OCSET
f
SW
R
=
OCSET
DETAILED OCP EQUATION
V
------------------------------- -
f
NUMBER OF HIGH SIDE MOSFETs
SW
SIMPLE OCP EQUATION
IN
=
Regulator Switching Frequency
=
- V
•
OCSET
DS(ON)
L
⎛
⎝
--------------------------------------------------------------------------------- -
=
OUT
OUT
I
OC_SOURCE
I
--------------------------------------------------------------- -
OC_SOURCE
µ
•
A pull-up keeps this REFIN pin
from the specification table
V
--------------- -
at the highest junction
V
OUT
I
HSOC
IN
8
200μA
+
•
I Δ
---- -
r •
2
N
⎞
⎠
DS ON
U
r •
(
DS ON
(
)
)
DS(ON)
OCSET
(EQ. 6)
ISL6535
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
A multi-layer printed circuit board is recommended. Figure 5
shows the critical components of the converter. Note that
capacitors C
physical capacitors. Dedicate one solid layer (usually a middle
layer of the PC board) for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. Keep the
metal runs from the PHASE terminals to the output inductor
short. The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the
remaining printed circuit layers for small signal wiring.
FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES
GND
ISL6535
KEY
UGATE
PHASE
LGATE
PGND
VIA CONNECTION TO GROUND PLANE
TRACE SIZED FOR 3A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE
ISLAND ON POWER PLANE LAYER
IN
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
BOOT
PVCC
VCC
AND ISLANDS
and C
SS
OUT
C
C
C
BP_PVCC
BP_VCC
SS
could each represent numerous
+12V
C
IN
Q
Q
1
2
L
VIN
OUT
C
C
OUT
IN
V
OUT
May 5, 2008
FN9255.1