ISL6741IBZ-T Intersil, ISL6741IBZ-T Datasheet - Page 14

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ISL6741IBZ-T

Manufacturer Part Number
ISL6741IBZ-T
Description
IC CTRLR PWM DBL-ENDED 16-SOIC
Manufacturer
Intersil
Datasheet

Specifications of ISL6741IBZ-T

Pwm Type
Current Mode
Number Of Outputs
2
Frequency - Max
2MHz
Duty Cycle
100%
Voltage - Supply
9 V ~ 16 V
Buck
No
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 105°C
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
2MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Fault Conditions
A fault condition occurs if V
input falls below 1.00V, the thermal protection is triggered, or
if OTS faults. When a fault is detected, OUTA and OUTB
outputs are disabled, the Fault signal is asserted, and the
soft-start capacitor is quickly discharged. When the fault
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins. The Fault signal is high
impedance during the soft-start cycle.
An overcurrent condition that results in shutdown (ISL6740),
or a short circuit shutdown also cause assertion of the Fault
signal. The difference between a current fault and the faults
described earlier is that the soft-start capacitor is not quickly
discharged. The initiation of a new soft-start cycle is delayed
while the soft-start capacitor is discharged at a 15μA rate.
This keeps the average output current to a minimum.
Thermal Protection
Two methods of over-temperature protection are provided.
The first method is an on board temperature sensor that
protects the device should the junction temperature exceed
145°C. There is approximately 15°C of hysteresis.
The second method uses an internal comparator with a 2.5V
reference (V
comparator is accessible through the OTS pin. A thermistor
or thermal sensor located at or near the area of interest may
be connected to this input. There is a nominal 25μA switched
current source used to create hysteresis. The current source
is active only during an OT fault; otherwise, it is inactive and
does not affect the node voltage. The magnitude of the
hysteresis is a function of the external resistor divider
impedance. Either a positive temperature coefficient (PTC)
or a negative temperature coefficient (NTC) thermistor may
be used. If a NTC is desired, position R1 may be substituted.
V
REF
REF
R1
R2
FIGURE 6. OTS HYSTERESIS
/2). The non-inverting input to the
R3
REF
14
V
REF
falls below 4.65V, the UV
25μA
V
REF
ON
/2
+
-
ISL6740, 1SL6741
If a PTC is desired, then position R2 may be substituted. The
threshold with increasing temperature is set by making the
fixed resistance equal in value to the thermistor resistance at
the desired trip temperature.
To determine the value of the hysteresis resistor, R3, select
the value of thermistor resistance that corresponds to the
desired reset temperature.
If the hysteresis resistor, R3, is not desired, the value of the
thermistor resistance at the reset temperature can be
determined from:
The OTS comparator may also be used to monitor signals
other than suggested above. It may also be used to monitor
any voltage signal for which an excess requires a response
as described above. Input or output voltage monitoring are
examples of this.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. V
be bypassed directly to GND with good high frequency
capacitance.
Typical Application
The Typical Application Schematic features the ISL6740 in
an unregulated half-bridge DC/DC converter configuration,
often referred to as a DC Transformer or Bus Regulator. The
ISL6740EVAL1 demonstration unit implements this design
and is available for evaluation.
The input voltage range is 48 ±10%VDC. The output is a
nominal 12V when the input voltage is at 48V. Since this is
an unregulated topology, the output voltage will vary
proportionately with input voltage. The load regulation is a
function of resistance between the source and the converter
output. The output is rated at 8A.
R3
R1
R2
V
TH
=
=
=
↑ = 2.5V and R1 = R2 (HOT)
10
--------------------------------------------------------------------- -
----------------------------------------
2.5 10
---------------------------------------- -
2.5
5
2.5 R2
2.5 R1
+
10
(
R1 R2
R1
5
5
R2
R1
+
R2
)
R1 R2
Ω
Ω
(
(
NTC
PTC
Ω
)
)
DD
July 13, 2007
(EQ. 12)
(EQ. 13)
(EQ. 11)
should
FN9111.4

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