ISL6244HRZ Intersil, ISL6244HRZ Datasheet

IC CTRLR PWM 2-4-PHASE 32-QFN

ISL6244HRZ

Manufacturer Part Number
ISL6244HRZ
Description
IC CTRLR PWM 2-4-PHASE 32-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6244HRZ

Pwm Type
Voltage/Current Mode
Number Of Outputs
4
Frequency - Max
4MHz
Duty Cycle
75%
Voltage - Supply
4.75 V ~ 5.25 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-10°C ~ 100°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Frequency-max
4MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Multi-Phase PWM Controller
The ISL6244 provides core-voltage regulation by driving 2 to
4 interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6244 uses cost and space-saving r
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 100mV using a single external
resistor. The entire system is trimmed to ensure a system
accuracy of ± 1%.
Outstanding features of this controller IC include
Dynamic VID
changing without the need of any external components.
Battery “feed-forward” is provided to allow for traditional
control schemes over total input voltage variation. Output
voltage “droop” or active voltage positioning is optional.
When employed, it allows the reduction in size and cost of
the output capacitors required to support load transients. A
threshold-sensitive enable input allows the use of an
external resistor divider for start-up coordination with Intersil
MOSFET drivers or any other devices powered from a
separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to reduce the output voltage.
Under-voltage conditions are detected, but PWM operation
is not disrupted. Over-current conditions cause a hiccup-
mode response as the controller repeatedly tries to restart.
After a set number of failed startup attempts, the controller
latches off. A power good logic signal indicates when the
converter output is between the UV and OV thresholds.
TM
technology allowing seamless on-the-fly VID
®
1
Data Sheet
DS(ON)
Copyright © Intersil Americas Inc. 2004 All Rights Reserved. Dynamic VID™ is a trademark of Intersil Americas Inc.
sensing
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Multi-Phase Power Conversion
• Active Channel Current Balancing
• Precision r
• Precision CORE Voltage Regulation
• Microprocessor Voltage Identification Input
• Programmable Droop Voltage
• Excellent Dynamic Response
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 4MHz)
• QFN Package:
• Pb-Free Available (RoHS Compliant)
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
December 28, 2004
- 2, 3 or 4 Phase Operation
- Lossless
- Low Cost
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
- ±1% System Accuracy
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID Technology
- Combined Input Voltage Feed-Forward and Pulse-by-
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
- Near Chip Scale Package footprint, which improves PCB
Pulse Average Current Mode
No Leads - Package Outline
efficiency and has a thinner profile
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
DS(ON)
Current Sharing
ISL6244
FN9106.3

Related parts for ISL6244HRZ

ISL6244HRZ Summary of contents

Page 1

... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 321-724-7143 Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004 All Rights Reserved. Dynamic VID™ trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. ISL6244 FN9106.3 ...

Page 2

... ISL6244CRZ 5x5 QFN (Note 1) (Pb-Free) ISL6244HR -10 to 100 32 Ld 5x5 QFN ISL6244HRZ -10 to 100 32 Ld 5x5 QFN (Note 1) (Pb-Free) NOTES: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

Page 3

Absolute Maximum Ratings Supply Voltage, VCC (Note .+7V Input, Output, or I/O Voltage ...

Page 4

Electrical Specifications Operating Conditions: VCC = 5V, T PARAMETER ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth Slew Rate Maximum Output Voltage Source Current Sink Current REMOTE-SENSE AMPLIFIER Input Impedance Bandwidth Slew Rate SENSE CURRENT IOUT Accuracy ISEN Offset Voltage Over-Current Trip ...

Page 5

Typical Operating Performance FIGURE 1. SOFT-START WAVEFORM FIGURE 3. INRUSH CURRENT AT VIN 10.8V @ 52A FIGURE 5. INDUCTOR CURRENT TRANSIENT 5 ISL6244 FIGURE 2. INRUSH CURRENT AT VIN 19V @ 52A FIGURE 4. TRANSIENT WAVEFORM FROM 0A TO 52A ...

Page 6

Typical Operating Performance 1.650 Vo+ (AMD SPEC) 1.600 1.550 1.500 Vo- (AMD SPEC) 1.450 1.400 0 20 OUTPUT CURRENT (A) FIGURE 7. ISL6244 DROOP: V 100 Vbat = 8.4 Vbat = 10.8 Vbat = 19 Vbat ...

Page 7

Functional Pin Description ISL6244CR (32 LEAD QFN 5x5) TOP VIEW VID2 1 2 VID1 VID0 OFS 6 COMP ...

Page 8

Typical Application: 3-Phase Buck Converter with r ISL6244 VCC VSEN RGND PWM4 VDIFF ISEN4 603 R FB 715 6800nF FB PWM1 C 12nF C IOUT R C ISEN1 2.43K COMP PWM2 OFS R ISEN2 OFS FS 2. PWM3 ...

Page 9

Theory of Operation Multi-Phase Power Conversion Microprocessor load current profiles have changed to the point where the multi-phase power conversion advantage is pronounced. The technical challenges associated with producing a single-phase converter which is both cost- VID4 VID3 DYNAMIC VID ...

Page 10

Interleaving The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle ...

Page 11

... Figure 16 illustrates Intersil’s patented current-balance method as implemented on channel multi-phase converter. (EQ. 3) sensing is not desired, an independent current- ...

Page 12

... The output of the error amplifier, V COMP sawtooth waveform to modulate the pulse width of the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. Three distinct inputs to the error amplifier determine the voltage level of V and external circuitry which control voltage regulation is illustrated in Figure 17 ...

Page 13

... DAC) plus offset errors in the OFS current source, remote- sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6244 to include all variations in current sources, amplifiers and the reference so that the output ...

Page 14

In most cases, each channel uses the same R sense current. A more complete expression for V derived by combining equations 15 and 16 OUT ------------ - ---------------------- R DROOP FB N ...

Page 15

... It is important that the driver ICs reach their POR level before the ISL6244 becomes enabled. The schematic in Figure 20 demonstrates sequencing the ISL6244 with the ISL620X family of Intersil MOSFET drivers which require 5V bias. The 11111 VID code is reserved as a signal to the controller that no load is present ...

Page 16

... The PWM outputs remain low until VDIFF falls to the programmed DAC level at which time they go into a high- impedance state. The Intersil drivers respond by turning off both upper and lower MOSFETs. If the over-voltage condition recurs, the ISL6244 will again command the lower MOSFETs to turn on ...

Page 17

... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications ...

Page 18

UPPER MOSFET POWER CALCULATION In addition to r losses, a large portion of the upper- DS(ON) MOSFET losses are due to currents conducted across the input voltage (V ) during switching. Since a substantially IN higher portion of the upper-MOSFET ...

Page 19

COMPENSATING LOAD-LINE REGULATED CONVERTER The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter L-C resonant frequency split with the introduction of current information into the control loop. The ...

Page 20

COMPENSATION WITHOUT LOAD-LINE REGULATION The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 26, ...

Page 21

Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output ...

Page 22

Figures 29 and 30 provide the same input RMS current information for three and four phase designs respectively. Use the same approach to selecting the bulk capacitor type and number as described above. 0 0.5 ...

Page 23

PHASE plane, is recommended. Stray Inductance in the switch path adds to the voltage spikes generated during the switching interval. By keeping the phase plane small, the magnitude ...

Page 24

V battery R OFS +5V OFS VFF PWM VCC C BP COMP C C ISL6244 VDIFF ISEN IOUT VSEN RGND GND ISLAND ON POWER PLANE LAYER KEY FIGURE 32. PRINTED CIRCUIT BOARD POWER PLANES AND ...

Page 25

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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