ISL6420AIRZ Intersil, ISL6420AIRZ Datasheet - Page 11

• Manufacturer Part Number: ISL6420AIRZ
• Description: IC CTRLR PWM SYNC BUCK 20-QFN
• Manufacturer: Intersil

Specifications of ISL6420AIRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.4MHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 28 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Frequency-max: 1.4MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VMSET/MODE - This pin is a dual function pin. Tie this pin to
VCC5 to disable voltage margining. When not tied to VCC5,
this pin serves as VMSET. Connect a resistor from this pin to
ground to set delta for voltage margining. If voltage
margining and external reference tracking mode are not
needed, this pin can be tied directly to ground.
GPIO2 - This is general purpose IO pin for voltage
margining. Refer to Table 2.
NOTES:
Functional Description
Initialization
The ISL6420A automatically initializes upon receipt of
power. The Power-On Reset (POR) function monitors the
internal bias voltage generated from LDO output (VCC5) and
the ENSS pin. The POR function initiates the soft-start
operation after the VCC5 exceeds the POR threshold. The
POR function inhibits operation with the chip disabled
(ENSS pin <1V).
The device can operate from an input supply voltage of 5.6V
to 28V connected directly to the VIN pin using the internal 5V
linear regulator to bias the chip and supply the gate drivers.
For 5V ±10% applications, connect VIN to VCC5 to bypass
the linear regulator.
Soft-Start/Enable
The ISL6420A soft-start function uses an internal current
source and an external capacitor to reduce stresses and
surge current during startup.
When the output of the internal linear regulator reaches the
POR threshold, the POR function initiates the soft-start
sequence. An internal 10µA current source charges an
external capacitor on the ENSS pin linearly from 0V to 3.3V.
Enable Voltage Margining
No Voltage Margining. Normal
operation using internal reference.
REFOUT not used.
No Voltage Margining. Normal
operation with internal reference.
Buffered V
No Voltage Margining. External
reference. Buffered V
V
1. The GPIO1/REFIN and GPIO2 pins cannot be left floating.
2. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.
REFIN
FUNCTION/MODES
REFOUT
= 0.6V.
REFOUT
TABLE 3. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION
=
11
Pin Connected
to GND with
resistor. It is
used as VMSET.
Pin Connected
to GND with
resistor. It is
used as VMSET
VMSET/MODE
H
H
Connect a 1µF
capacitor for
bypass of external
reference.
Connect a 1µF
capacitor for
bypass of external
reference.
Connect a 2.2µF
capacitor to GND.
Connect a 2.2µF
capacitor to GND.
REFOUT
PIN CONFIGURATIONS
ISL6420A
Serves as a general
purpose I/O. Refer to
Table 2
Connect to an external
reference voltage
source (0.6V to 1.25V)
When the ENSS pin voltage reaches 1V typically, the
internal 0.6V reference begins to charge following the dv/dt
of the ENSS voltage. As the soft-start pin charges from 1V to
1.6V, the reference voltage charges from 0V to 0.6V.
Figure 9 shows a typical soft-start sequence.
GPIO1/REFIN
TABLE 2. VOLTAGE MARGINING CONTROLLED BY GPIO1
H
L
GPIO1
FIGURE 9. TYPICAL SOFT-START WAVEFORM
H
H
L
L
V
AND GPIO2
IN
= 28V, V
Serves as a
general purpose
I/O. Refer to
Table 2
OUT
GPIO2
L
L
L
= 3.3V, I
GPIO2
H
H
L
L
OUT
REFIN or REFOUT functions
will not be available in this
mode. The internal 0.6V
reference is used.
= 10A
COMMENTS
+ Delta VOUT
- Delta VOUT
No Change
Ignored
VOUT
October 13, 2005
FN9169.1