HIP6006CB Intersil, HIP6006CB Datasheet - Page 7

• Manufacturer Part Number: HIP6006CB
• Description: IC CTRLR PWM VOLTAGE MODE 14SOIC
• Manufacturer: Intersil

Specifications of HIP6006CB

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 215kHz
• Duty Cycle: 100%
• Voltage - Supply: 2.5 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 215kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6006) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F
F
Z1
Z2
∆V
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
F
o
LC
OSC
. The equations below relate the compensation
=
=
FB
=
----------------------------------
2π R
----------------------------------------------------- -
2π
. The goal of the compensation network is to provide
OSC
-------------------------------------- -
2π
•
•
•
(
0dB
R1
COMPARATOR
1
2 C1
COMPENSATION DESIGN
ERROR
AMP
L
V
1
•
HIP6006
) and adequate phase margin. Phase margin
O
+
1
E/A
DETAILED COMPENSATION COMPONENTS
PWM
R3
•
Z
+
C
-
COMP
+
FB
-
) C3
O
C1
•
REFERENCE
C2
+
-
R2
DRIVER
DRIVER
Z
REF
7
F
IN
F
F
ESR
P1
P2
Z
FB
FB
=
=
=
V
----------------------------------
2π R3 C3
------------------------------------------------------ -
2π R2
IN
-------------------------------------------- -
2π
PHASE
•
C3
•
(PARASITIC)
•
(
1
Z
ESR C
L
IN
O
R1
•
1
•
R3
1


ESR
C1 C2
--------------------- -
C1
C
•
V
O
OUT
+
•
O
0dB
C2
)
V
OUT


and
IN
HIP6006
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak do to the high Q factor of the output filter and is
not shown in Figure 8. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the log-log graph of Figure 8 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with -
20dB/decade slope and a phase margin greater than 45
Include worst case component variations when determining
phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
100
-20
-40
-60
80
60
40
20
(~75% F
0
and Z
10
(R2/R1)
20LOG
IN
MODULATOR
ST
ND
ST
ND
LC
to provide a stable, high bandwidth (BW) overall
100
Zero Below Filter’s Double Pole
Pole at the ESR Zero
)
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
GAIN
1K
F
Z1
F
FREQUENCY (Hz)
LC
F
Z2
10K
F
P1
F
(V
ESR
100K
IN
20LOG
F
/
∆
P2
V
OSC
P2
OPEN LOOP
ERROR AMP GAIN
1M
)
with the
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M
o
.