ISL6525CB Intersil, ISL6525CB Datasheet - Page 6

• Manufacturer Part Number: ISL6525CB
• Description: IC CTRLR VRM8.5 PWM 14-SOIC
• Manufacturer: Intersil

Specifications of ISL6525CB

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 215kHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 215kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R
presence of switching noise on the input voltage.
Programming PGOOD Delay Time
The PGOOD rising edge delay can be programmed by
connecting a small capacitor C
and GND. The rising-edge delay is determined by the 10µA
discharging current source I
between VCC and the gate threshold voltage V
drain FET, and the capacitor value. The delay time t
be calculated with the following equation,
V
1nF of C
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 6 should be located as close together as possible.
t
2. The minimum I
3. Determine
DELAY
OCSET
TH
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
where ∆I is the output inductor ripple current.
ISL6525
is typically 2V, VCC is 12V, and I
=
DELAY
to smooth the voltage across R
C
-----------------------------------------------------------
PHASE
UGATE
LGATE
PGND
DELAY
GROUND PLANES OR ISLANDS
I
PEAK
leads to 1ms of delay time typically.
I
DISCH
(
OCSET
VCC V
for I
–
PEAK
from the specification table.
DISCH
Q2
V
Q1
TH
RETURN
IN
DELAY
6
)
>
I
, the voltage difference
D2
OUT MAX
between the DELAY pin
(
DISCH
C
OCSET
IN
)
L
+
O
is 10µA. Thus,
(
TH
∆I
C
O
) 2 ⁄
in the
of the open-
V
DELAY
OUT
,
can
ISL6525
Please note that the capacitors C
numerous physical capacitors. Locate the ISL6525 within 3
inches of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the ISL6525
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
close to the SS pin because the internal current source is
only 10µA. Provide local V
GND pins. Locate the capacitor, C
to the BOOT and PHASE pins.
∆V
C
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
SS
SS
OSC
OSC
ISL6525
GND
COMPARATOR
LAYOUT GUIDELINES
COMPENSATION DESIGN
ERROR
AMP
V
ISL6525
E/A
DETAILED COMPENSATION COMPONENTS
PWM
Z
+
-
COMP
FB
+
-
C1
PHASE
C
VCC
BOOT
BOOT
REFERENCE
+12V
C2
+
CC
-
R2
DRIVER
DRIVER
REF
C
Z
decoupling between VCC and
IN
VCC
D1
IN
BOOT
Z
and C
FB
FB
V
IN
PHASE
as close as practical
O
C3
Q1
(PARASITIC)
+V
Q2
each represent
Z
IN
L
IN
R1
L
O
O
R3
ESR
December 27, 2004
C
O
C
V
O
OUT
V
FN4998.3
OUT
V
OUT
ss