ISL6564CR-T Intersil, ISL6564CR-T Datasheet - Page 14

• Manufacturer Part Number: ISL6564CR-T
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6564CR-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MOSFET r
The controller can also sense the channel load current by
sampling the voltage across the lower MOSFET r
(see Figure 6). The amplifier is ground-reference by
connecting the ISEN- input to the source of the lower
MOSFET. ISEN+ connects to the PHASE node through a
resistor R
the voltage drop across the r
while it is conducting. The resulting current into the ISEN+
pin is proportional to the channel current I
current is then sampled and held after sufficient settling time.
The sampled current I
load-line regulation, and overcurrent protection. From
Figure 6, Equation 7 for I
where I
increases with temperature, a PTC resistor should be
chosen for R
I
SEN
FIGURE 6. MOSFET r
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
SAMPLE
ISL6564 INTERNAL CIRCUIT
HOLD
=
ISL6564 INTERNAL CIRCUIT
&
I
L
n
I
I
L
is the channel current. Since MOSFET r
SEN
ISEN
SAMPLE
r
----------------------
I
HOLD
DS(ON)
SEN
DS ON
R
&
ISEN
I
ISEN
n
=
(
. The voltage across R
I
=
L
)
I
r
------------------------- -
to compensate for this change.
+
L
-
SENSING
DS ON
R
R SENSE
------------------------- -
ISEN
R
(
n
ISEN
DS(ON)
, is used for channel-current balance,
SEN
+
-
)
DS(ON)
14
ISEN+(n)
ISEN-(n)
CURRENT-SENSING CIRCUIT
is derived.
EXTERNAL CIRCUIT
R
ISEN-(n)
ISEN+(n)
(PTC)
L
ISEN
of the lower MOSFET
ISEN
R
I
SENSE
L
V
L
IN
is equivalent to
. The ISEN
+
-
R
I
L
ISEN(n)
C
N-CHANNEL
MOSFETs
r
V
DS ON
OUT
OUT
I
L
DS(ON)
DS(ON)
(
)
(EQ. 7)
ISL6564
Channel-Current Balance
The sampled currents I
summed together and divided by the number of active
channels. The resulting cycle average current I
a measure of the total load current demand on the converter
during each switching cycle. Channel current balance is
achieved by comparing the sampled current of each channel
to the cycle average current, and making an appropriate
adjustment to each channel pulse width based on the error.
Intersil’s patented current-balance method is illustrated in
Figure 7, with error correction for channel 1 represented. In
the figure, the cycle average current combines with the
channel 1 sample, I
filtered error signal modifies the pulse width commanded by
V
The same method for error signal correction is applied to
each active channel.
NOTE: *Channels 3 and 4 are optional.
Channel current balance is essential in realizing the thermal
advantage of multi-phase operation. The heat generated in
down converting is dissipated over multiple devices and a
greater area. The designer avoids the complexity of driving
multiple parallel MOSFETs, and the expense of using heat
sinks and nonstandard magnetic materials.
Voltage Regulation
The integrating compensation network shown in Figure 8
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6564 to include the
combined tolerances of each of these elements.
The output of the error amplifier, V
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry which control
voltage regulation is illustrated in Figure 8.
COMP
FIGURE 7. CHANNEL-1 PWM FUNCTION AND CURRENT-
V
COMP
to correct any unbalance and force I
FILTER
BALANCE ADJUSTMENT
+
I
ER
-
+
f(jω)
I
1
1
, to create an error signal I
-
n
I
AVG
, from each active channel are
SAWTOOTH SIGNAL
÷ N
COMP
+
-
, is compared to the
Σ
ER
AVG
December 27, 2004
ER
toward zero.
. The
PWM1
I
I
I
, provides
4
3
2
*
*
FN9156.2