ISL8103CRZ Intersil, ISL8103CRZ Datasheet
ISL8103CRZ
Specifications of ISL8103CRZ
Related parts for ISL8103CRZ
ISL8103CRZ Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8103 FN9246 ...
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... Ordering Information PART NUMBER PART MARKING ISL8103CRZ* (Note) ISL8103 CRZ ISL8103IRZ* (Note) ISL8103 IRZ * Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Block Diagram ICOMP DROOP ISEN AMP ISUM IREF RGND VSEN x1 x1 VDIFF UVP OVP OVP +150mV x 0.82 REF1 DAC REF0 DAC REF E/A FB COMP OFST OFFSET 3 ISL8103 OCSET PGOOD OVP 100µA OC +1V SOFT-START AND FAULT ...
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Typical Application - ISL8103 FB VDIFF VSEN RGND 3PH +5V 2PH VCC OFST FS DAC ISL8103 REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP OCSET ICOMP 4 ISL8103 +12V COMP PVCC1 BOOT1 UGATE1 PHASE1 ISEN1 LGATE1 +12V PVCC2 ...
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... VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL8103CRZ 0°C to +70°C Ambient Temperature (ISL8103IRZ .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER ERROR AMPLIFIER DC Gain (Note 3) ...
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Timing Diagram t PDHUGATE UGATE LGATE t FLGATE Simplified Power System Diagram +12V IN + REF0,REF1 ENLL OVP PGOOD Functional Pin Description VCC (Pin 6) Bias supply for the IC’s small-signal circuitry. Connect this pin to a +5V ...
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REF0 and REF1 (Pins 40, 39) These pins make up the 2-bit input that selects the fixed DAC reference voltage. These pins respond to TTL logic thresholds. The ISL8103 decodes these inputs to establish one of four fixed reference voltages; ...
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PHASE1, PHASE2, and PHASE3 (Pins 29, 28, 22) Connect these pins to the sources of the upper MOSFETs. These pins are the return path for the upper MOSFETs’ drives. LGATE1, LGATE2, and LGATE3 (Pins 34, 23, 17) These pins are ...
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... Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current- balance method is illustrated in Figure 3, with error correction for Channel 1 represented. In the figure, the cycle ...
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V COMP + - - SAWTOOTH SIGNAL FILTER f( AVG ÷ NOTE: Channel 2 and 3 are optional. FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT- BALANCE ADJUSTMENT Current Sampling In ...
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... DAC or the external voltage reference) and offset errors in the OFS current source, remote sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL8103 to include the combined tolerances of each of these elements, except when an external reference or voltage divider is used, then the tolerances of these components has to be taken into account ...
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The droop voltage created by sensing the DROOP current through the output inductors. This is accomplished by using a continuous DCR current sensing method. Inductor windings have a characteristic distributed resistance or DCR (Direct Current Resistance). For ...
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VDIFF + V R OFS 1 VREF - FB I OFS OFS ISL8103 R OFS GND FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE PROGRAMMING VDIFF - V R OFS 1 VREF + FB I OFS VCC R OFS OFS ISL8103 FIGURE ...
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Q = 100nC GATE 0.4 50nC 0.2 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 ΔV BOOT_CAP FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE Gate Drive Voltage Versatility The ISL8103 provides the user ...
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DAC 1280 + ------------------------------------------- - For example, a regulator with 450kHz switching frequency having REF voltage set to 1.2V has 100mV offset exists on the remote-sense amplifier at the beginning ...
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Undervoltage Detection The undervoltage threshold is set at 82% of the REF voltage. When the output voltage (VSEN-RGND) is below the undervoltage threshold, PGOOD gets pulled low. No other action is taken by the controller. PGOOD will return high if ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for many applications. ...
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Package Power Dissipation When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controller. Since there are a total of three drivers in the controller package, the total power ...
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Current Balancing Component Selection The ISL8103 senses the channel load current by sampling the voltage across the lower MOSFET r Figure 17. The ISEN pins are denoted ISEN1, ISEN2, and ISEN3. The resistors connected between these pins and the respective ...
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FIGURE 18. TIME CONSTANT MISMATCH BEHAVIOR Compensation The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in “Load-Line (Droop) Regulation” on page ...
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Compensating the Converter operating without Load-Line Regulation The ISL8103 multiphase converter operating without load line regulation behaves in a similar manner to a voltage-mode controller. This section highlights the design consideration for a voltage-mode controller requiring external compensation. To address ...
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Calculate C such that F is placed ------------------------------------------------------- - C = ⋅ ⋅ ⋅ 2 2π – Calculate R such that F is placed at ...
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Equation 36. di ΔV ≈ ⋅ ΔI ⋅ ESL ---- - + ESR dt The filter capacitor must have sufficiently low ESL and ESR ...
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L,P-P L,P 0. L,P-P O L,P-P 0.2 0 0.2 0.4 0.6 DUTY CYCLE (V FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER For a three-phase design, use Figure ...
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MOSFETs using short, high current pulses important to size them as large and as short as possible to reduce their overall impedance and inductance. Extra care should be given to the LGATE traces in particular since keeping the ...
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VDIFF VSEN RGND 3PH +5V 2PH VCC C HF0 R OFST OFST DAC ISL8103 R REF REF C REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...