LTC1703CG#TRPBF Linear Technology, LTC1703CG#TRPBF Datasheet - Page 30

IC REG SW DUAL SYNC VID 28SSOP

LTC1703CG#TRPBF

Manufacturer Part Number
LTC1703CG#TRPBF
Description
IC REG SW DUAL SYNC VID 28SSOP
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1703CG#TRPBF

Applications
Controller, Mobile Intel Pentium® III
Voltage - Input
3 ~ 7 V
Number Of Outputs
2
Voltage - Output
0.9 ~ 2 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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APPLICATIO S I FOR ATIO
LTC1703
capacitors and/or paralleling multiple capacitors at the
output. The capacitance value accounts for the rest of the
voltage drop until the inductor current rises. With most
output capacitors, several devices paralleled to get the
ESR down will have so much capacitance that this drop
term is negligible. Ceramic capacitors are an exception; a
small ceramic capacitor can have suitably low ESR with
relatively small values of capacitance, making this second
drop term significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC1703 to
recover after the output voltage has dropped due to output
capacitor ESR. Optimizing loop compensation entails
maintaining the highest possible loop bandwidth while
ensuring loop stability. The Feedback Component Selec-
tion section describes in detail how to design an optimized
feedback loop, appropriate for most LTC1703 systems.
Voltage Positioning
If the load transients consist primarily of load steps from
near zero load to full load and back, the transient response
can be traded off against DC regulation performance by
using a technique known as “voltage positioning.” The
30
Figure 17c. Voltage Positioning Regulator
LTC1703
Figure 17a. Standard Regulator
LTC1703
FB
FB
U
V
V
IN
IN
U
W
R
VP
1703 F17a
V
OUT
1703 F17c
V
OUT
U
CURRENT
CURRENT
Figure 17b. Standard Regulator—Transient Response
Figure 17d. Positioning Regulator—Transient Response
LOAD
LOAD
V
V
OUT
OUT
goal is to intentionally compromise the DC regulation loop
such that the output rides near the maximum allowable
value (often +5%) with no load and near the minimum
allowable value at maximum load. With the load at zero,
any transient that comes along will be a current increase
which will cause the output voltage to fall. Since the output
voltage is initially at a high value, it can fall further before
it goes out of spec. Similarly, at full load, the output current
can only decrease, causing a positive shift in the output
voltage; the initial low value allows it to rise further before
the spec is exceeded. The primary benefit of voltage
positioning is it increases the allowable ESR of the output
capacitors, saving cost. An additional bonus is that at
maximum load, the output voltage is near the minimum
allowable, decreasing the power dissipated in the load.
Implementing voltage positioning is as simple as creating
an intentional resistance in the output path to generate the
required voltage drop. This resistance can be a low value
resistor, a length of PCB trace, or even the parasitic
resistance of the inductor if an appropriate filter is used. If
the LTC1703 senses the output voltage upstream from the
resistance (Figure 17c), the output voltage will move with
load as I • R
value of the voltage positioning resistor. If the feedback
network is then reset to regulate near the upper edge of the
NOM
NOM
+5%
–5%
MAX
+5%
–5%
MAX
0
0
VP
, where I is the load current and R
1703 F17b
1703 F17d
MAXIMUM
ALLOWABLE
TRANSIENT
MAXIMUM
ALLOWABLE
TRANSIENT
≈2× FIGURE 17b
VP
is the
1703fa

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