ISL6556ACBZ Intersil, ISL6556ACBZ Datasheet - Page 19

• Manufacturer Part Number: ISL6556ACBZ
• Description: IC CTRLR MULTIPHASE VRM10 28SOIC
• Manufacturer: Intersil

Specifications of ISL6556ACBZ

• Applications: Controller, Intel VR10X
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 4
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the measured temperature rise above the ambient
temperature. While a single adjustment according to Equation
18 is usually sufficient, it may occasionally be necessary to
adjust R
balance between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R
Its value depends on the desired full-load droop voltage
(V
ISEN resistor, the load-line regulation resistor is as shown
in Equation 19.
If one or more of the ISEN resistors is adjusted for thermal
balance, as in Equation 18, the load-line regulation resistor
should be selected according to Equation 20 where I
full-load operating current and R
connected to the n
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
R
R
R
FB
DROOP
FB
ISEN 2 ,
=
=
--------------------------------
I
V
------------------------ -
ISEN
70 10
FL
V
DROOP
=
in Figure 5). If Equation 17 is used to select each
DROOP
×
r
DS ON
R
two or more times to achieve optimal thermal
ISEN
-6
(
)
th
ΔT
----------
ΔT
∑
n
ISEN pin.
2
1
R
ISEN n ( )
19
C
and C
ISEN(n)
C
.
is the ISEN resistor
FB
in Figure 5.
(EQ. 18)
FL
(EQ. 20)
(EQ. 19)
is the
ISL6556A
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equations 21, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
Case 2:
Case 1:
Case 3:
FIGURE 12. COMPENSATION CONFIGURATION FOR
R
FB
LOAD-LINE REGULATED ISL6556A CIRCUIT
R
C
-------------------
2π LC
f
R
C
0
C
C
V
C
C
R
C
+
-------------------
2π LC
1
>
-
DROOP
R
=
=
C
C
----------------------------- -
2πC ESR
=
=
C
1
R
------------------------------------------------------------ -
(
=
=
R
0.75V
------------------------------------------------ -
2π
≤
C
FB
2πV
FB
FB
R
2
----------------------------------- -
2πV
(
f
1
)
0
C
>
(OPTIONAL)
FB
V
--------------------------------------------
2
, has already been chosen as
C
0.75V
<
----------------------------------------- -
0.75 V
f
PP
PP
f
0
IN
0
PP
2πf
----------------------------------- -
----------------------------- -
2πC ESR
0.75V
2
0.75 V
2π f
)
(
R
(
V
0.75V
2π
ESR
R
FB
0
PP
IN
FB
(
V
0
IN
1
)
COMP
VDIFF
2
IN
V
f
pp
R
IOUT
0
f
(
pp
IN
) C
0
f
FB
ESR
FB
0
IN
2
L
L
LC
)
LC
LC
0
)
. The target
(EQ. 21)
0