ISL6236AIRZ-T Intersil, ISL6236AIRZ-T Datasheet - Page 8

• Manufacturer Part Number: ISL6236AIRZ-T
• Description: IC MAIN PWR CTRLR QUAD 32-QFN
• Manufacturer: Intersil

Specifications of ISL6236AIRZ-T

• Applications: Controller, Notebook Computers
• Voltage - Input: 4.5 ~ 25 V
• Number Of Outputs: 4
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

Pin Descriptions
Typical Performance Curves
100
FIGURE 1. V
90
80
70
60
50
40
30
20
10
PIN
0
21
22
23
24
25
26
27
28
29
30
31
32
0.001
7V
7V
7V
12V
12V
IN
IN
IN
IN
IN
SKIP MODE
PWM MODE
ULTRA SKIP MODE
PHASE2
UGATE2
LGATE2
REFIN2
BOOT2
SKIP MODE
PWM MODE
OUT2
NAME
PGND
POK2
OUT2
ILIM2
SKIP
GND
EN2
0.010
= 1.05V EFFICIENCY vs LOAD (300kHz)
(Continued)
OUTPUT LOAD (A)
Analog Ground for both SMPS and LDO. Connect externally to the underside of the exposed pad.
Power Ground for SMPS controller. Connect PGND externally to the underside of the exposed pad.
SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC.
Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the “Typical Application
Circuits” on page 19 (Figures 66, 67 and 68). See “MOSFET Gate Drivers (UGATE, LGATE)” on page 29.
Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver.
PHASE2 is the current-sense input for the SMPS2.
High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE1 swings between PHASE2 and BOOT2.
SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than
the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start). Drive
EN2 below 0.8V to clear fault level and reset the fault latches.
SMP2 Power-Good Open-Drain Output. POK2 is low when the SMPS2 output voltage is more than 10% below the
normal regulation point or during soft-start. POK2 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK2 is low in shutdown.
Low-Noise Mode Control. Connect SKIP to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM
mode (fixed frequency). Connect to REF or leave floating for ultrasonic skip mode operation.
SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. OUT2 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode.
SMPS2 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM2 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM2. Connect ILIM2 to REF for a fixed 200mV.
The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V.
Output voltage control for SMPS2. Connect REFIN2 to VCC for fixed 3.3V. Connect REFIN2 to VREF3 for fixed 1.05V.
REFIN2 can be used to program SMPS2 output voltage from 0.5V to 2.50V. SMPS2 output voltage is 0V if
REFIN2 < 0.5V.
8
0.100
12V
25V
25V
25V
IN
IN
IN
IN
ULTRA SKIP MODE
SKIP MODE
PWM MODE
ULTRA SKIP MODE
1.000
Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, V
EN2 = EN1 = VCC, V
otherwise noted. Typical values are at T
10.000
ISL6236A
BYP
= 5V, PVCC = 5V, V
FUNCTION
100
FIGURE 2. V
90
80
70
60
50
40
30
20
10
0
0.001
A
7V
7V
7V
12V
12V
= +25°C.
IN
IN
IN
IN
IN
SKIP MODE
PWM MODE
ULTRA SKIP MODE
EN_LDO
OUT1
SKIP MODE
PWM MODE
0.010
= 1.5V EFFICIENCY vs LOAD (200kHz)
= 5V, T
OUTPUT LOAD (A)
A
= -40°C to +100°C, unless
0.100
REF3
12V
25V
25V
25V
, and REF, V
IN
IN
IN
IN
ULTRA SKIP MODE
SKIP MODE
PWM MODE
ULTRA SKIP MODE
1.000
IN
March 18, 2008
= 12V,
FN6453.3
10.000