ISL6266AHRZ Intersil, ISL6266AHRZ Datasheet - Page 8

• Manufacturer Part Number: ISL6266AHRZ
• Description: IC CORE CTRLR 2PHASE 48-QFN
• Manufacturer: Intersil

Specifications of ISL6266AHRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PGOOD - Power good open-drain output. Connect
externally with 680Ω to VCCP or 1.9kΩ to 3.3V.
PSI# - Current indicator input. When asserted low, indicates
a reduced load-current condition and initiates single-phase
operation.
PMON - Analog output. PMON is proportional to the product
of Vsen and droop voltage.
RBIAS - 147kΩ resistor to VSS sets internal current
reference.
VR_TT# - Thermal overload output indicator with open-drain
output. Over-temperature pull-down resistance is 10Ω.
NTC - Thermistor input to VRTT# circuit and a 60µA current
source is connected internally to this pin.
SOFT - A capacitor from this pin to GND sets the maximum
slew rate of the output voltage. SOFT is the non-inverting
input of the error amplifier.
OCSET - Overcurrent set input. A resistor from this pin to
VO sets DROOP voltage limit for OC trip. A 10µA current
source is connected internally to this pin.
VW - A resistor from this pin to COMP programs the
switching frequency (for example, 6.45kΩ ≅ 400kHz).
COMP - This pin is the output of the error amplifier.
FB - This pin is the inverting input of error amplifier.
FB2 - There is a switch between FB2 pin and the FB pin.
The switch is closed in single-phase operation and is
opened in two phase operation. The components connecting
to FB2 are to adjust the compensation in single phase
operation to achieve optimum performance.
VDIFF - This pin is the output of the differential amplifier.
VSEN - Remote core voltage sense input.
RTN - Remote core voltage sense return.
DROOP - Output of the droop amplifier. The voltage level on
this pin is the sum of V
DFB - Inverting input to droop amplifier.
VO - An input to the IC that reports the local output voltage.
VSUM - This pin is connected to the summation junction of
channel current sensing.
VIN - Battery supply voltage. It is used for input voltage feed
forward to improve input line transient performance.
VSS - Signal ground. Connect to local controller ground.
VDD - 5V control power supply.
ISEN2 - Individual current sharing sensing for Channel 2.
ISEN1 - Individual current sharing sensing for Channel 1.
O
and the droop voltage.
8
ISL6266, ISL6266A
N/C - Not connected. Grounding this pin to signal ground in
the practical layout.
BOOT2 - This pin is the upper gate driver supply voltage for
Phase 2. An internal boot strap diode is connected to the
PVCC pin.
UGATE2 - Upper MOSFET gate signal for Phase 2.
PHASE2 - The phase node of Phase 2. Connect this pin to
the source of the Channel 2 upper MOSFET.
PGND2 - The return path of the lower gate driver for
Phase 2.
LGATE2 - Lower-side MOSFET gate signal for Phase 2.
PVCC - 5V power supply for gate drivers.
LGATE1 - Lower-side MOSFET gate signal for Phase 1.
PGND1 - The return path of the lower gate driver for
Phase 1.
PHASE1 - The phase node of phase 1. Connect this pin to
the source of the Channel 1 upper MOSFET.
UGATE1 - Upper MOSFET gate signal for Phase 1.
BOOT1 - This pin is the upper-gate-driver supply voltage for
Phase 1. An internal boot strap diode is connected to the
PVCC pin.
VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with
VID0 is the least significant bit (LSB) and VID6 is the most
significant bit (MSB).
VR_ON - Digital enable input. A logic high signal on this pin
enables the regulator.
DPRSLPVR - Deeper sleep enable signal. A logic high
signal on this pin indicates the micro-processor is in
deeper-sleep mode and also indicates a slow C4 entry or
exit rate with 41µA discharging or charging the SOFT
capacitor.
DPRSTP# - Deeper sleep slow wake up signal. A logic low
signal on this pin indicates the micro-processor is in
deeper-sleep mode.
CLK_EN# - Digital output for system clock. Goes active
10µs after V
3V3 - 3.3V supply voltage for CLK_EN#.
CORE
is within 10% of Boot voltage.
June 14, 2010
FN6398.3