ISL6262CRZ-TK Intersil, ISL6262CRZ-TK Datasheet - Page 27

IC CORE CTRLR 2PHASE 48-QFN

ISL6262CRZ-TK

Manufacturer Part Number
ISL6262CRZ-TK
Description
IC CORE CTRLR 2PHASE 48-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6262CRZ-TK

Applications
Converter, Intel IMVP-6
Voltage - Input
5 ~ 25 V
Number Of Outputs
1
Voltage - Output
0.3 ~ 1.5 V
Operating Temperature
-10°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
48-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SEATING PLANE
(DATUM A)
INDEX
AREA
AREA
(DATUM B)
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
INDEX
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
AREA
6
6
A
NX L
C
1
2
3
8
3
2
1
N
TOP VIEW
N
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
D
5
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
D/2
NX b
D2
2
BOTTOM VIEW
SECTION "C-C"
SIDE VIEW
For information regarding Intersil Corporation and its products, see www.intersil.com
(Nd-1)Xe
D2
REF.
2X
27
0.15
NX b
e
C
A1
A
5
E/2
N
0.10
7
A3
E
B
NX k
E2/2
2X
M C
8
A1
0.15
E2
A
A
7
C
B
/ /
(Ne-1)Xe
B
0.08
0.10 C
REF.
C
ISL6262
8
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C)
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
6. The configuration of the pin #1 identifier is optional, but must be
7. Dimensions D2 and E2 are for the exposed pads which provide
8. Nominal dimensions are provided to assist with PCB Land Pattern
SYMBOL
between 0.15mm and 0.30mm from the terminal tip.
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
improved electrical and thermal performance.
Design efforts, see Intersil Technical Brief TB389.
A1
A3
D2
E2
Nd
Ne
A
D
E
N
b
e
k
L
0.80
0.18
4.15
4.15
0.25
0.30
MIN
-
MILLIMETERS
NOMINAL
7.00 BSC
7.00 BSC
0.20 REF
0.50 BSC
0.90
0.23
4.30
4.30
0.40
48
12
12
-
-
MAX
1.00
0.05
0.30
4.45
4.45
0.50
-
Rev. 2 5/06
May 15, 2006
NOTES
FN9199.2
5, 8
7, 8
7, 8
8
2
3
3
-
-
-
-
-
-
-

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