ISL6261ACRZ Intersil, ISL6261ACRZ Datasheet - Page 14

• Manufacturer Part Number: ISL6261ACRZ
• Description: IC CORE CTRLR 1PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6261ACRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 21 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Efficiency Operation Mode
The operational modes of the ISL6261A depend on the
control signal states of DPRSTP#, FDE, and DPRSLPVR, as
shown in Table 2. These control signals can be tied to lntel
IMVP-6
configuration for all IMVP-6
DPRSTP# = 0, FDE = 0 and DPRSLPVR = 1 enables the
ISL6261A to operate in Diode Emulation Mode (DEM) by
monitoring the low-side FET current. In diode emulation
mode, when the low-side FET current flows from source to
drain, it turns on as a synchronous FET to reduce the
conduction loss. When the current reverses its direction, trying
to flow from drain to source, the ISL6261A turns off the
low-side FET to prevent the output capacitor from discharging
through the inductor, therefore eliminating the extra
conduction loss. When DEM is enabled, the regulator works in
automatic Discontinuous Conduction Mode (DCM), meaning
that the regulator operates in CCM in heavy load, and
operates in DCM in light load. DCM in light load decreases the
switching frequency to increase efficiency. This mode can be
used to support the deeper sleep mode of the microprocessor.
DPRSTP# = 0 and FDE = 1 enables the Enhanced Diode
Emulation Mode (EDEM), which increases the VW-COMP
window voltage by 33%. This further decreases the
switching frequency at light load to boost efficiency in the
deeper sleep mode.
For other combinations of DPRSTP#, FDE, and
DPRSLPVR, the ISL6261A operates in forced CCM.
The ISL6261A operational modes can be set according to
CPU mode signals to achieve the best performance. There
are two options: (1) Tie FDE to DPRSLPVR, and tie
DPRSTP# and DPRSLPVR to the corresponding CPU mode
signals. This configuration enables EDEM in deeper sleep
mode to increase efficiency. (2) Tie FDE to “1” and
DPRSTP# to “0” permanently, and tie DPRSLPVR to the
corresponding CPU mode signal. This configuration sets the
regulator in EDEM all the time. The regulator will enter DCM
Overcurrent fault
Way-Overcurrent fault
Overvoltage fault (1.7V)
Overvoltage fault (+200mV)
Undervoltage fault (-300mV)
Over-temperature fault (NTC<1.18) Immediately
®
control signals to maintain the optimal system
FAULT TYPE
®
14
conditions.
120µs
<2µs
Immediately
1ms
1ms
PRIOR TO PROTECTION
FAULT DURATION
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6261A
ISL6261A
®
PWM tri-state, PGOOD latched low
PWM tri-state, PGOOD latched low
(OV-1.7V always)
VR_TT# goes high
PWM tri-state, PGOOD latched low
Low-side FET on until Vcore < 0.85V, then
PWM tri-state, PGOOD latched low
PWM tri-state, PGOOD latched low
PROTECTION ACTIONS
based on load current. Light-load efficiency is increased in
both active mode and deeper sleep mode.
CPU mode-transition sequences often occur in concert with
VID changes. The ISL6261A employs carefully designed
mode-transition timing to work in concert with the VID changes.
The ISL6261A is equipped with internal counters to prevent
control signal glitches from triggering unintended mode
transitions. For example: Control signals lasting less than
seven switching periods will not enable the diode emulation
mode.
Dynamic Operation
The ISL6261A responds to VID changes by slewing to new
voltages with a dv/dt set by the SOFT capacitor and the logic of
DPRSLPVR. If C
voltage will move at a maximum dv/dt of ±10mV/μs for large
changes. The maximum dv/dt can be used to achieve fast
recovery from Deeper Sleep to Active mode. If C
and DPRSLPVR = 1, the output voltage will move at a dv/dt of
±2mV/μs for large changes. The slow dv/dt into and out of
deeper sleep mode will minimize the audible noise. As the
output voltage approaches the VID command value, the dv/dt
moderates to prevent overshoot. The ISL6261A is IMVP-6
compliant for DPRSTP# and DPRSLPVR logic.
Intersil R
High-speed input voltage transients have little effect on the
output voltage.
Intersil R
transients to achieve fast response. Upon load application,
the ISL6261A will transiently increase the switching
frequency to deliver energy to the output more quickly.
Compared with steady state operation, the PWM pulses
during load application are generated earlier, which
effectively increases the duty cycle and the response speed
of the regulator. Upon load release, the ISL6261A will
transiently decrease the switching frequency to effectively
reduce the duty cycle to achieve fast response.
3
3
™ has an intrinsic voltage feed forward function.
™ commands variable switching frequency during
SOFT
= 20nF and DPRSLPVR = 0, the output
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VDD toggle
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
N/A
FAULT RESET
SOFT
December 21, 2007
= 20nF
FN6354.2
®