EL5326IRZ-T13 Intersil, EL5326IRZ-T13 Datasheet - Page 9

• Manufacturer Part Number: EL5326IRZ-T13
• Description: IC VREF GEN 12CH TFT-LCD 28TSSOP
• Manufacturer: Intersil

Specifications of EL5326IRZ-T13

• Applications: Converter, TFT, LCD
• Voltage - Input: 5 ~ 16.5 V
• Number Of Outputs: 12
• Voltage - Output: 0.5 ~ 14.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Analog Section
TRANSFER FUNCTION
The transfer function is:
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5226 and EL5326 will be
derived from the reference voltages present at the V
and V
about 32kΩ.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5226 and EL5326. GND < V
V
In some LCD applications that require more than 12
channels, the system can be designed such that one
EL5226 or EL5326 will provide the Gamma correction
voltages that are more positive than the V
second EL5226 or EL5326 can provide the Gamma
correction voltage more negative than the V
The Application Drawing shows a system connected in this
way.
CLOCK OSCILLATOR
The EL5226 and EL5326 require an internal clock or external
clock to refresh its outputs. The outputs are refreshed at the
V
2
REFH
FIGURE 11. START, STOP & TIMING DETAILS OF I
OUT IDEAL )
C Timing Diagram 2
R3
0
0
0
0
REGISTER ADDRESS
CONDITION
(
REFH
START
.
t
S
R2
0
0
0
1
t
H
pins. The impedance between those two pins is
INTERFACE
=
t
R
V
REFL
R1
t
0
0
1
1
S
+
data
------------ -
1024
R0
t
H
0
1
0
1
t
F
×
REFH
9
(
V
D9
REFH
0
1
0
1
CLOCK
≤ V
DATA
S
- V
D8
and GND ≤ V
0
0
0
1
COM
REFL
t
R
COM
STOP CONDITION
potential. The
)
D7
0
0
0
1
2
potential.
C
REFL
REFL
EL5226, EL5326
D6
t
0
0
0
1
F
≤
D5
0
0
0
1
DATA
falling OSC clock edges. The output refreshed switches open
at the rising edges of the OSC clock. The driving load shouldn’t
be changed at the rising edges of the OSC clock. Otherwise, it
will generate a voltage error at the outputs. This clock may be
input or output via the clock pin labeled OSC. The internal clock
is provided by an internal oscillator running at approximately
21kHz and can be output to the OSC pin. In a 2 chip system, if
the driving loads are stable, one chip may be programmed to
use the internal oscillator; then the OSC pin will output the clock
from the internal oscillator. The second chip may have the OSC
pin connected to this clock source.
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
After power on, the chip will start with the internal oscillator
mode. At this time, the OSC pin will be in a high impedance
condition to prevent contention. By setting pin 32 to high, the
chip is on external clock mode. Setting pin 32 to low, the chip
is on internal clock mode.
D4
0
0
1
1
D3
0
0
1
1
D2
0
0
1
1
D1
0
0
1
1
D0
0
0
1
1
Channel A, Value = 0
Channel B, Value = 512
Channel C, Value = 31
Channel H, Value = 1023
CONDITION