EL5325IREZ Intersil, EL5325IREZ Datasheet - Page 5

• Manufacturer Part Number: EL5325IREZ
• Description: IC VOLT GEN 12CH TFT-LCD 28TSSOP
• Manufacturer: Intersil

Specifications of EL5325IREZ

• Applications: Converter, TFT, LCD
• Voltage - Input: 5 ~ 16.5 V
• Number Of Outputs: 12
• Voltage - Output: 0.5 ~ 14.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Typical Performance Curves
General Description
The EL5325 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5325,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5325. As all of the output
buffers are identical, it is also possible to use the EL5325 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V
FIGURE 9. POWER DISSIPATION vs AMBIENT
200mV
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
5V
0V
5V
0V
0V
0
0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
833mW
TO 200mV)
TEMPERATURE
M=400µs/DIV
25
AMBIENT TEMPERATURE (°C)
50
5
75
85
SCLK
(Continued)
SDA
OUTPUT
100
125
EL5325
Digital Interface
The EL5325 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5325 can support
the clock rate up to 5MHz.
Serial Interface
The EL5325 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB (bit
15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
FIGURE 10. POWER DISSIPATION vs AMBIENT
FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM
1.4
1.2
0.8
0.6
0.4
0.2
M=400µs/DIV
1
0
0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.333W
200mV TO 0V)
TEMPERATURE
25
OUTPUT
AMBIENT TEMPERATURE (°C)
50
75
SCLK
SDA
85
100
125