ISL6262IRZ Intersil, ISL6262IRZ Datasheet - Page 16

• Manufacturer Part Number: ISL6262IRZ
• Description: IC CORE CTRLR 2PHASE 48-QFN
• Manufacturer: Intersil

Specifications of ISL6262IRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

resistance of the inductors as shown in the application circuit
of Figure 26. In both cases signals representing the inductor
currents are summed at VSUM, which is the non-inverting
input to the DROOP amplifier shown in the block diagram of
Figure 1. The voltage at the DROOP pin minus the output
voltage, VO´, is a high-bandwidth analog of the total inductor
current. This voltage is used as an input to a differential
amplifier to achieve the IMVP-6 load line, and also as the
input to the overcurrent protection circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus maintaining the load-
line accuracy.
In addition to monitoring the total current (used for DROOP
and overcurrent protection), the individual channel average
currents are also monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to
cause the voltages presented at the ISEN pins to be equal.
The ISL6262 controller can be configured for two-channel
operation, with the channels operating 180 degrees apart.
The channel PWM frequency is determined by the value of
R
Figure 27. Input and output ripple frequencies will be the
channel PWM frequency multiplied by the number of active
channels.
High Efficiency Operation Mode
The ISL6262 has several operating modes to optimize
efficiency. The controller's operational modes are designed
to work in conjunction with the Intel IMVP-6 control signals to
maintain the optimal system configuration for all IMVP-6
conditions. These operating modes are established by the
IMVP-6 control signal inputs such as PSI#, DPRSLPVR, and
DPRSTP# as shown in Table 2. At high current levels, the
system will operate with both phases fully active, responding
rapidly to transients and deliver the maximum power to the
load. At reduced load current levels, one of the phases may
COMPLIANT LOGIC
FSET
OTHER LOGIC
COMMANDS
Intel IMVP-6
connected to pin VW as shown in Figure 26 and
DPRSLPVR
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6262
0
0
1
1
0
0
1
1
16
DPRSTP#
1
1
0
0
0
0
1
1
PSI#
1
0
1
0
1
0
1
0
ISL6262
2-phase CCM
1-phase CCM
1-phase diode emulation
1-phase diode emulation
2-phase CCM
1-phase CCM
2-phase CCM
1-phase CCM
PHASE OPERATION MODES
be idled. This configuration will minimize switching losses,
while still maintaining transient response capability. At the
lowest current levels, the controller automatically configures
the system to operate in single-phase automatic-DCM
mode, thus achieving the highest possible efficiency. In this
mode of operation, the lower FET will be configured to
automatically detect and prevent discharge current flowing
from the output capacitor through the inductors, and the
switching frequency will be proportionately reduced, thus
greatly reducing both conduction and switching losses.
Smooth mode transitions are facilitated by the R
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms which robustly
maintain voltage-regulation for all control signal input
sequences and durations.
Mode-transition sequences will often occur in concert with
VID changes; therefore the timing of the mode transitions of
ISL6262 has been carefully designed to work in concert with
VID changes. For example, transitions into single-phase
mode will be delayed until the VID induced voltage ramp is
complete, to allow the associated output capacitor charging
current is shared by both inductor paths. While in single-
phase automatic-DCM mode, VID changes will initiate an
immediate return to two-phase CCM mode. This ensures
that both inductor paths share the output capacitor charging
current and are fully active for the subsequent load current
increases.
spurious control signal glitches from resulting in unwanted
mode transitions. Control signals of less than two switching
periods do not result in phase-idling. Signals of less than 7
switching periods do not result in implementation of
automatic-DCM mode.
The controller contains internal counters which prevent
active mode
active mode
deeper sleep mode
deeper sleep mode
EXPECTED CPU MODE
3
May 15, 2006
FN9199.2