ISL6312CRZ-T Intersil, ISL6312CRZ-T Datasheet - Page 25

• Manufacturer Part Number: ISL6312CRZ-T
• Description: IC CTRLR PWM 4PHASE BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6312CRZ-T

• Applications: Controller, Intel VR10, VR11, AMD CPU
• Voltage - Input: 5 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.38 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

turns on the lower MOSFET to control the output voltage
until the overvoltage event ceases or the input power supply
cuts off. For complete protection, the low side MOSFET
should have a gate threshold well below the maximum
voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Undervoltage Detection
The undervoltage threshold is set at 60% of the VID code.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 70% of the VID code.
Open Sense Line Prevention
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6312 is designed to prevent the
controller from regulating. This is accomplished by means of
a small 5µA pull-up current on VSEN, and a pull-down
current on RGND. If the sense lines are opened at any time,
the voltage difference between VSEN and RGND will
increase until an overvoltage event occurs, at which point
overvoltage protection activates and the controller stops
regulating. The ISL6312 will be latched off and cannot be
restarted until the controller is reset.
Overcurrent Protection
The ISL6312 takes advantage of the proportionality between
the load current and the average current, I
overcurrent condition. See “Continuous Current Sampling”
on page 12 for more detail on how the average current is
measured. The average current is continually compared with
a constant 125µA OCP reference current as shown in
Figure 14. Once the average current exceeds the OCP
reference current, a comparator triggers the converter to
begin overcurrent protection procedures.
This method for detecting overcurrent events limits the
minimum overcurrent trip threshold because of the fact the
ISL6312 uses set internal R
The minimum overcurrent trip threshold is dictated by the
DCR of the inductors and the number of active channels. To
calculate the minimum overcurrent trip level, I
Equation 21, where N is the number of active channels, DCR
is the individual inductor’s DCR, and R
internal current sense resistor.
If the desired overcurrent trip level is greater then the
minimum overcurrent trip level, I
divider R-C circuit around the inductor shown in Figure 5
should be used to set the desired trip level.
I
OCP min
,
=
125 10
--------------------------------------------------------- -
⋅
–
DCR
6
⋅
R
ISEN
ISEN
25
⋅
N
OCP,min
current sense resistors.
ISEN
, then the resistor
AVG
is the 300Ω
OCP,min
, to detect an
(EQ. 21)
, use
ISL6312
The overcurrent trip level of the ISL6312 cannot be set any
lower then the I
overcurrent trip level lower then I
ISL6312A should be used in the place of the ISL6312.
At the beginning of overcurrent shutdown, the controller sets
all of the UGATE and LGATE signals low, puts PWM4 in a
high-impedance state, and forces PGOOD low. This turns off
all of the upper and lower MOSFETs. The system remains in
this state for fixed period of 12ms. If the controller is still
enabled at the end of this wait period, it will attempt a soft-
start. If the fault remains, the trip-retry cycles will continue
indefinitely until either the controller is disabled or the fault is
cleared. Note that the energy delivered during trip-retry
cycling is much less than during full-load operation, so there
is no thermal hazard.
Individual Channel Overcurrent Limiting
The ISL6312 has the ability to limit the current in each
individual channel without shutting down the entire regulator.
This is accomplished by continuously comparing the sensed
currents of each channel with a constant 170μA OCL
reference current as shown in Figure 14. If a channel’s
individual sensed current exceeds this OCL limit, the UGATE
signal of that channel is immediately forced low, and the
LGATE signal is forced high. This turns off the upper
MOSFET(s), turns on the lower MOSFET(s), and stops the
rise of current in that channel, forcing the current in the
channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel current falls
back below the 170µA reference.
I
I
OCP
OCP
FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE
0A
0V
>
=
I
OCP min
⎛
⎜
⎝
125 10
--------------------------------------------------------- -
OUTPUT CURRENT, 50A/DIV
,
⋅
OUTPUT VOLTAGE,
500mV/DIV
OCP,min
–
DCR
6
⋅
R
ISEN
level calculated above. If an
⋅
N
3ms/DIV
⎞
⎟
⎠
⋅
⎛
⎜
⎝
R
-------------------- -
OCP,min
1
R
+
2
R
2
⎞
⎟
⎠
is desired, then the
February 1, 2011
(EQ. 22)
FN9289.6