ISL6425ER Intersil, ISL6425ER Datasheet - Page 10

• Manufacturer Part Number: ISL6425ER
• Description: IC REG DUAL LNBP TTL-INP 32-QFN
• Manufacturer: Intersil

Specifications of ISL6425ER

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

NOTE: OTF is a “Read Only” bit and X indicates a “Don’t Care” condition for the function specified.
Received Data (
The ISL6425 can provide to the master a copy of the System
Register information via the I
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6425 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
• Not acknowledge, stopping the read mode
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6425.
These bits are read as they were
after the last write operation.
DCL ISEL ENT LLC VSEL EN OTF OLF
transmission of another byte from the ISL6425.
communication.
SR1
SR2
0
0
0
0
0
0
0
0
0
0
0
0
1
TABLE 6. READING SYSTEM REGISTERS
DCL
X
X
X
X
X
X
X
X
X
1
0
X
X
-
I
ISEL1
2
C
X
X
X
X
X
X
X
X
X
X
X
0
1
-
Bus Read Mode)
ENT1
2
10
X
X
X
X
X
0
1
X
X
X
X
X
X
C bus in read mode. The read
-
0
1
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION
LLC1
0
1
X
X
X
X
X
X
X
X
0
0
0
1
1
-
Tj ≤ 130°C, Normal
operation
Tj > 150°C, Power
blocks disabled
Iout < Imax, Normal
operation
Iout > Imax, Overload
protection triggered
VSEL1
FUNCTION
EN2
X
X
X
X
X
X
X
0
0
1
0
1
0
EN1
OTF
X
X
1
1
1
1
1
1
1
1
1
1
0
ISL6425
OLF1
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Power-On I
The I
at power-on. The I
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I
system register SR is initialized to all zeros, thus keeping the
power blocks disabled.
SR1 is selected
Vout1 = 13V, Vboost1 = 13V + Vdrop
Vout1 = 18V, Vboost1 = 18V + Vdrop
Vout1 = 14V, Vboost1 = 14V + Vdrop
Vout1 = 19V, Vboost1 = 19V + Vdrop
22kHz tone is controlled by the DSQIN pin
22kHz tone is ON, the DSQIN input is disabled
Iout1 = 425mA max.
Iout1 = 775mA max.
Dynamic current limit NOT selected
Dynamic current limit selected
PWM and Linear for channel 1 disabled
SR2 is selected; to read OTF flag.
2
C interface built into the ISL6425 is automatically reset
2
C Interface Reset
2
C interface block will receive a Power OK
FUNCTION
FUNCTION
2
C commands and the
February 8, 2005
FN9176.1