LTC3728LEGN-1#PBF Linear Technology, LTC3728LEGN-1#PBF Datasheet - Page 14

IC REG SYNC DUAL 28-SSOP

LTC3728LEGN-1#PBF

Manufacturer Part Number
LTC3728LEGN-1#PBF
Description
IC REG SYNC DUAL 28-SSOP
Manufacturer
Linear Technology
Series
PolyPhase®r
Type
Step-Down (Buck)r
Datasheet

Specifications of LTC3728LEGN-1#PBF

Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
2
Voltage - Output
0.8 ~ 7 V
Current - Output
3A
Frequency - Switching
250kHz ~ 550kHz
Voltage - Input
4.5 ~ 28 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC3728LEGN-1#PBF
Manufacturer:
LT
Quantity:
189
APPLICATIONS INFORMATION
LTC3728L-1
25% of the current limit determined by R
inductor values (higher ΔI
lower load currents, which can cause a dip in effi ciency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Usually, high inductance is preferred for small current
ripple and low core loss. Unfortunately, increased induc-
tance requires more turns of wire or a smaller air gap in
the inductor core, resulting in high copper loss or low
saturation current. Once the value of L is known, the actual
inductor must be selected. There are two popular types
of core material of commercial available inductors. Ferrite
core inductors usually have very low core loss and are
preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing satura-
tion. However, ferrite core saturates “hard”, which means
that inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. One advantage of the LTC3728L-1 is its current
mode control that detects and limits cycle-by-cycle peak
inductor current. Therefore, accurate and fast protection
is achieved if the inductor is saturated in steady state or
during transient mode.
Powdered iron core inductors usually saturate “soft”, which
means the inductance drops in a linear fashion when the
current increases. However, the core loss of the powder
iron inductor is usually higher than the ferrite inductor.
So designs with high switching frequency should also
address inductor core loss.
Inductor manufacturers usually provide inductance, DCR,
(peak) saturation current and (DC) heating current ratings
in the inductor data sheet. A good supply design should
not exceed the saturation and heating current rating of
the inductor.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller in the LTC3728L-1: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
14
L
) will cause this to occur at
SENSE
. Lower
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
voltage. This voltage is typically 5V during start-up
(see EXTV
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (V
< 5V); then, sub-logic level threshold MOSFETs (V
< 3V) should be used. Pay close attention to the BV
specifi cation for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
voltage and maximum output current. Miller capacitance,
C
usually provided on the MOSFET manufacturers’ data
sheet. C
along the horizontal axis while the curve is approximately
fl at divided by the specifi ed change in V
then multiplied by the ratio of the application applied V
to the Gate charge curve specifi ed V
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
The MOSFET power dissipations at maximum output
current are given by:
MILLER
Main Switch Duty Cycle =
P
P
Synchronous Switch Duty Cycle =
MAIN
SYNC
, can be approximated from the gate charge curve
MILLER
=
=
( )
CC
V
V
V
V
IN
V
INTVCC
OUT
IN
DS(ON)
Pin Connection). Consequently, logic-level
IN
2
– V
V
is equal to the increase in gate charge
IN
(
I
I
MAX
OUT
MAX
, Miller capacitance C
1
– V
2
)
(
THMIN
2
I
MAX
(
(
R
1+
DR
)
V
+
2
V
)
OUT
)
(
(
IN
V
R
1+
C
THMIN
DS(ON)
MILLER
1
)
DS
R
V
IN
DS(ON)
. When the IC is
DS
+
)
( )
– V
V
f
. This result is
MILLER
IN
OUT
, input
GS(TH)
3728l1fc
DSS
DS
CC
IN

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