ISL65426HRZS2715 Intersil, ISL65426HRZS2715 Datasheet
ISL65426HRZS2715
Specifications of ISL65426HRZS2715
Related parts for ISL65426HRZS2715
ISL65426HRZS2715 Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006-2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL65426 FN6340 ...
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Pinout 2 ISL65426 ISL65426 (50 LD QFN) TOP VIEW PGND 1 42 PGND 2 41 PGND 3 40 PGND LX1 38 LX1 PVIN1 36 PVIN2 8 ...
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Typical Application Schematics 3. 1. FIGURE 1. TYPICAL APPLICATION FOR 3A:3A CONFIGURATION 3 ISL65426 SINGLE INPUT SUPPLY 3.3V 3.3V PVIN1 PVIN2 PVIN3 LX1 LX2 ISL65426 LX3 FB1 3.3V PVIN6 3.3V PVIN5 C4 PVIN4 LX6 L2 2.5V ...
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Typical Application Schematics 5. 1. FIGURE 2. TYPICAL APPLICATION FOR 4A:2A CONFIGURATION 4 ISL65426 (Continued) DUAL INPUT SUPPLY 3.3V 5.0V PVIN1 PVIN2 PVIN3 PVIN4 ISL65426 LX1 LX2 LX3 LX4 FB1 3.3V PVIN6 3.3V PVIN5 C4 LX6 ...
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Typical Application Schematics 5. 2.5V 5A FIGURE 3. TYPICAL APPLICATION FOR 5A:1A CONFIGURATION 5 ISL65426 (Continued) 5.0V 5.0V PVIN1 PVIN2 PVIN3 PVIN4 PVIN6 ISL65426 LX1 LX2 LX3 LX4 LX6 FB1 5.0V PVIN5 5. LX5 ...
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Functional Block Diagram SOFT-START FB1 V1SET1 OUTPUT VOLTAGE V1SET2 CONFIG PGOOD1 PWM REFERENCE 0.60V SOFT-START FB2 V2SET1 OUTPUT VOLTAGE CONFIG V2SET2 6 ISL65426 EN2 EN VCC GND POWER-ON RESET (POR) SLOPE COMPENSATION PWM EA GM CONTROL LOGIC COMPENSATION UV POWER-GOOD ...
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... Ambient Temperature Range (ISL65426HRZ .-10°C to +100°C Ambient Temperature Range (ISL65426IRZA .-40°C to +85°C Operating Junction Temperature Range . . . . . . . . .-10°C to +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = -40°C to +85°C for ISL65426IRZA. (Note 5) A TEST CONDITIONS EN1 = EN2 = EN = VCC = 5V, I ...
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Electrical Specifications Recommended operating conditions, unless otherwise noted. VCC = PVIN = 5.0V -10°C to +100°C for ISL65426HRZ and T A PARAMETER Upper Device r DS(ON) Lower Device r DS(ON) Efficiency POWER-ON RESET AND ENABLE PINS VCC POR ...
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Typical Performance Curves 100 3.3V 5. 0.1 1.0 2.0 OUTPUT LOAD (A) FIGURE 1.2V EFFICIENCY vs LOAD OUT1 100 5. ...
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Typical Performance Curves 1.235 1.225 1.215 5.5V IN 1.205 1.195 1.185 2.5V IN 1.175 1.165 0.1 1.0 2.0 OUTPUT LOAD (A) FIGURE 10 1.2V REGULATION vs LOAD OUT1 1.545 1.535 1.525 5.5V 1.515 1.505 1.495 1.485 2.5V 1.475 ...
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Typical Performance Curves 1.845 1.825 1.805 1.785 5.5V IN 1.765 1.745 0.1 0.5 1.0 OUTPUT LOAD (A) FIGURE 16 1.8V REGULATION vs LOAD OUT2 2.565 2.545 2.525 2.505 2.485 2.465 2.445 2.425 0.1 0.5 1.0 OUTPUT LOAD (A) ...
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Typical Performance Curves EN1 5V/DIV PG1 5V/DIV FIGURE 22. START- 1.2V (NO LOAD) OUT1 EN1 5V/DIV PG1 5V/DIV FIGURE 24. START- 1.2V (FULL LOAD) OUT1 EN2 5V/DIV PG2 5V/DIV FIGURE 26. START- 3.3V (NO ...
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Typical Performance Curves EN2 5V/DIV PG2 5V/DIV FIGURE 28. START- 3.3V (FULL-LOAD) OUT2 V RIPPLE 20mV/DIV OUT1 I 500mA/DIV OUT1 V RIPPLE 50mV/DIV OUT2 FIGURE 30 1.2V LOAD TRANSIENT OUT1 LX1 5V/DIV V 500mV/DIV OUT1 IL1 ...
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Typical Performance Curves FIGURE 34 PGND 1 PGND 2 PGND 3 PGND 4 5 LX1 6 LX1 7 PVIN1 PGND PVIN2 8 LX2 9 10 PGND 11 PGND 12 LX3 PVIN3 13 ...
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EN System enable for voltage monitoring with programmable hysteresis. This pin has a POR rising threshold of 0.6V. This enable is intended for applications where two or more input power supplies are used and bias rise time is an issue. ...
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Table 2. When each pin is pulled to GND by an internal 10µA pull-down, this default condition programs the output voltage to the lowest level. The pull-down prevents situations where a pin could be left floating for example (cold ...
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Equation 2. R VCC2 and R is the resistor from EN to GND. 2 0.6V ⋅ ------------ + 10μA + 0.6V ENABLE Once the voltage at the EN pin ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides a complete reference design that includes schematics, a bill of materials and example board layout. Output Filter Design ...
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Equation 4. di ΔV ≈ × [ × ΔI ] ESL ---- - ESR + dt The filter capacitors selected must have sufficiently low ESL and ESR so ...
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The following multi-layer printed circuitry board layout strategies minimize the impact of board parasitics on converter performance and optimize the heat-dissipating capabilities of the printed circuit board. This section highlights some important practices which should not be overlooked during the ...
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Sensitive signals should be routed on different layers or some distance away from the PHASE plane on the same layer. Crosstalk due to switching noise is reduced into these lines by isolating the routing path away from the PHASE plane. ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...